Semiconductor memory device and controller
According to one embodiment, a semiconductor memory device includes a plurality of blocks. The blocks includes a first selection transistor, a second selection transistor, a plurality of memory cell transistors, a first selection gate line and a second selection gate line, and word lines. One of the blocks holds information on a word line, a first selection gate line and/or a second selection gate line including a short-circuiting defect.
1. A semiconductor memory system comprising:
a memory device including a memory cell array which comprises a plurality of blocks; and
a controller configured to output a first command and a second command, the controller being configured to output the first command when one of the blocks which includes a short-circuiting defect is accessed, and the controller being configured to output the second command when one of the blocks without a short-circuiting defect is accessed;
wherein the memory device is configured to perform a read operation when a same voltage is applied to at least two lines including the short-circuiting defect when the memory device receives the first command and a read command.
2. The system according to claim 1 , wherein each of the blocks comprises:
a first selection transistor and a second selection transistor;
a plurality of memory cell transistors each including a charge accumulation layer and a control gate and stacked above a semiconductor substrate, the memory cell transistors being connected in series between the first selection transistor and the second selection transistor;
a first selection gate line and a second selection gate line connected to gates of the first selection transistor and the second selection transistor, respectively;
word lines connected to gates of the respective memory cell transistors; and
a source line to which one end of a conductive path of a first selection transistor is connected; and
wherein when the one of the blocks including the short-circuiting defect is accessed, the controller outputs the first command to set interconnects including the short-circuiting defect to an identical potential.
3. The system according to claim 2 , wherein the processor, upon accessing the block including the short-circuiting defect, outputs a third command to rewrite a register of the memory device, the third command relating to voltages to be applied to the word lines.
4. The system according to claim 2 , wherein when the first selection gate line and the second selection gate line are short-circuited on the one of the blocks, the controller outputs the first command to set the first selection gate line and the second selection gate line to the identical potential.
5. The system according to claim 2 , wherein when adjacent ones of the first selection gate lines are short-circuited on the one of the blocks, the controller outputs the first command to set the adjacent ones of the first selection gate lines to the identical potential.
6. The system according to claim 2 , wherein when adjacent ones of the second selection gate lines are short-circuited on the one of the blocks, the controller outputs the first command to set the adjacent ones of the second selection gate lines to the identical potential.
7. The system according to claim 2 , wherein when adjacent ones of the word lines are short-circuited on the one of the blocks, the controller outputs the first command to set the adjacent ones of the word lines to the identical potential.
8. The system according to claim 2 , wherein when the source line and the first selection gate line are short-circuited on the one of the blocks, the controller outputs the first command to set the source line and the first selection gate line to the identical potential.
9. The system according to claim 1 , wherein the controller comprises:
a processor which outputs the read command to access the memory device; and
a memory unit which holds data.
10. The system according to claim 9 , wherein when the memory device is powered on, the controller receives information on the short-circuiting defect from the memory device and the processor outputs a third command to hold the information in the memory unit.
11. The system according to claim 10 , wherein the controller determines whether or not any of the blocks includes a defect, and outputs the first command to write the information based on a result of the determination in an area of the memory device which is different from a ROM fuse.
12. The system according to claim 11 , wherein the controller outputs a fourth command to erase data from one of the blocks and determines whether or not the defect is present in the one of the blocks based on a status observed when the data is erased.
13. The controller according to claim 11 , wherein the memory device is a NAND flash memory, and the controller outputs an inter-word-line leakage check command specified by a NAND interface to determine whether or not the defect is present.
14. The system according to claim 9 , wherein when the memory device is powered on, the controller receives information regarding a bad block from the memory device, and
wherein the processor, upon receiving a request to access the block including the short-circuiting defect, reads information on the short-circuiting defect from the memory device and outputs a third command to hold the information on the short-circuiting defect in the memory unit.
15. A semiconductor memory system comprising:
a memory cell array including a plurality of blocks, each of the blocks including a plurality of memory cell transistors stacked above a semiconductor substrate and connected in series and a plurality of word lines connected to respective gates of the memory cell transistors; and
a controller which controls data access to the memory cell array,
wherein when a word line short-circuiting defect occurs in the block, the controller outputs a first command to divide the word lines in the block into a plurality of regions to manage the blocks.
16. The system according to claim 15 , wherein:
the plurality of regions are arranged along a stacking direction of the memory cell transistors,
a region containing no word line with a short-circuiting defect is managed as a good region, and
a region containing a word line with the short-circuiting defect is managed as a defect region.
17. The system according to claim 16 , wherein the controller outputs a second command to data-access the good region, and to avoid data-accessing the defect region.
18. The system according to claim 17 , further comprising a ROM fuse which stores information on the defect region in a nonvolatile manner, wherein the controller outputs a third command to use the information stored in the ROM fuse to control voltages of the word lines so as to set the defect region to an unselected state.
19. The system according to claim 18 , wherein the controller outputs the third command to use the information on the defect region read from the ROM fuse and to avoid accessing the defect region.
20. The system according to claim 19 , further comprising a memory unit which stores the information on the defect region.