Overflow detection and correction in state machine engines
State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.
1. A state machine engine, comprising:
a state machine lattice comprising a plurality of configurable elements;
a storage location configured to store data to be transmitted to the state machine lattice; and
an inter-rank (IR) bus control system configured to receive an indication of an amount of data locations being utilized in the storage location of the state machine engine and transmit a halt signal configured to halt a write operation of the state machine engine based, at least in part, on the amount of data locations being utilized in the storage location.
2. The state machine engine of claim 1 , wherein the IR bus control system is configured to compare the indication with a threshold.
3. The state machine engine of claim 2 , wherein the IR bus control system is configured to generate the halt signal as indicative of an overflow condition based, at least in part, on whether the indication meets or exceeds the threshold.
4. The state machine engine of claim 2 , wherein the IR bus control system is configured to determine if any of the data locations are available in the storage location based, at least in part, on whether the indication meets or exceeds the threshold.
5. The state machine engine of claim 4 , wherein the IR bus control system is configured to transmit an indication to allow writing of data to the determined available data locations.
6. The state machine engine of claim 1 , wherein the IR bus control system is configured to monitor a transmission of the data from the storage location.
7. The state machine engine of claim 6 , wherein the IR bus control system is configured to transmit a restart signal based, at least in part, on a status of the transmission of the data from the storage location.
8. The state machine engine of claim 6 , wherein the IR bus control system is configured to transmit a restart signal if the transmission of the data from the storage location is complete.
9. The state machine engine of claim 8 , wherein the state machine engine initializes a second write operation based, at least in part, on the restart signal.
10. The state machine engine of claim 1 , wherein the storage location comprises a buffer.
11. The state machine engine of claim 10 , wherein the buffer comprises a data buffer.
12. The state machine engine of claim 10 , wherein the buffer comprises a process buffer.
13. The state machine engine of claim 1 , wherein the storage location comprises a register.
14. A device, comprising:
a first state machine engine, comprising:
a first state machine lattice comprising a plurality of configurable elements;
a first storage location configured to store data to be transmitted to the first state machine lattice; and
a first inter-rank (IR) bus control system configured to receive a first indication of an amount of data locations being utilized in the first storage location of the first state machine engine and transmit a first halt signal configured to halt a write operation of the first state machine engine based, at least in part, on the first indication of the amount of data locations being utilized in the first storage location;
a second state machine engine, comprising:
a second state machine lattice comprising a plurality of configurable elements;
a second storage location configured to store data to be transmitted to the second state machine lattice; and
a second IR bus control system configured to receive a second indication of an amount of data locations being utilized in the second storage location of the second state machine engine and transmit a second halt signal configured to halt a write operation of the second state machine engine based, at least in part, on the second indication of the amount of data locations being utilized in the second storage location; and
a communication bus coupled to the first state machine engine and the second state machine engine.
15. The device of claim 14 , wherein the device is configured to designate the first state machine engine as a master element and designate the second state machine engine as a slave element.
16. The device of claim 15 , wherein the communication bus is configured to transmit a common clock signal to both the first state machine engine and the second state machine engine.
17. The device of claim 16 , wherein the first IR bus control system and the second IR bus control system are configured to simultaneously transmit the first halt signal and the second halt signal based, at least in part, on the common clock signal.
18. The device of claim 17 , wherein the first IR bus control system and the second IR bus control system transmit first data from the data locations being utilized in the first storage location and second data from the data locations being utilized in the second storage location, respectively, subsequent to transmission of the first halt signal and the second halt signal.
19. The device of claim 18 , wherein the first IR bus control system and the second IR bus control system are each configured to transmit a restart signal respectively to the first state machine engine and the second state machine engine based, at least in part, on a status of the transmission of the first data and the second data.
20. The device of claim 19 , wherein, wherein the first state machine engine initializes a second write operation based, at least in part, on the restart signal.
21. The device of claim 20 , wherein the second state machine engine initializes a second write operation concurrently with the second write operation of the first state machine.
22. A state machine engine, comprising an inter-rank (IR) bus control system configured to halt a write operation of data from an IR bus and process buffer interface to a state machine lattice, wherein the state machine lattice comprises a plurality of configurable elements and each of the plurality of configurable elements comprises a plurality of memory cells configured to analyze the data and to output a result of the analysis.
23. The state machine engine of claim 22 , wherein the IR bus control system is configured to monitor a transmission of the data from the state machine engine.
24. A state machine engine, comprising:
an inter-rank (IR) bus control system configured to halt a write operation of data to a state machine lattice, wherein the state machine lattice comprises a plurality of configurable elements and each of the plurality of configurable elements comprises a plurality of memory cells configured to analyze the data and to output a result of the analysis; and
a storage location configured to store the data, wherein the IR bus control system is configured to halt the write operation based, at least in part, on an indication of an amount of data locations being utilized in the storage location.
25. The state machine engine of claim 24 , wherein the IR bus control system is configured to determine if any of the data locations are available in the storage location and transmit an indication to allow writing of additional data to the available data locations prior to halting the write operation.
26. The state machine engine of claim 24 , wherein the storage location comprises a buffer.
27. The state machine engine of claim 24 , wherein the storage location comprises a register.
28. A state machine engine, comprising an inter-rank (IR) bus control system configured to halt a write operation of data to a state machine lattice, wherein the state machine lattice comprises a plurality of configurable elements and each of the plurality of configurable elements comprises a plurality of memory cells configured to analyze the data and to output a result of the analysis, wherein the IR bus control system is configured to monitor a transmission of the data from the state machine engine, wherein the IR bus control system is configured to initialize a second write operation based, at least in part, on the transmission of the data from the state machine engine.
29. A method, comprising:
storing data in a storage location to be transmitted to a state machine lattice;
receiving at an inter-rank (IR) bus control system an indication of an amount of data locations being utilized in the storage location; and
transmitting from the IR bus control system a halt signal configured to halt a write operation based, at least in part, on the indication of the amount of data locations being utilized in the storage location.
30. The method of claim 29 , comprising comparing the indication with a threshold.
31. The method of claim 30 , comprising generating the halt signal as indicative of an overflow condition based, at least in part, on whether the indication meets or exceeds the threshold.
32. The method of claim 30 , comprising determining if any of the data locations are available in the storage location based, at least in part, on whether the indication meets or exceeds the threshold.
33. The method of claim 32 , comprising transmitting an indication to allow writing of data to the determined available data locations.
34. The method of claim 29 , comprising monitoring transmission of data from the data locations of the storage location.
35. The method of claim 34 , comprising transmitting a restart signal based, at least in part, on a status of the transmission of data.
36. The method of claim 34 , comprising transmitting a restart signal if the transmission of data is complete.
37. The method of claim 36 , comprising initializing a second write operation based, at least in part, on the restart signal.