IP Library Granted Patent US 8,773,193
Granted Patent B2
US 8,773,193 · App. 13/839,310 · Granted Jul 8, 2014

Methods, devices, and systems for switched capacitor array control

Inventor: Arthur S. Morris, III (Raleigh, NC)
Assignee: wiSpry, Inc.
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Quick Facts
Patent No.
US 8,773,193
App. No.
13/839,310
Granted
Jul 8, 2014
Kind
B2
Abstract

The present subject matter relates to methods, devices, and systems for switched array control. For an array of two-state elements that can be independently positioned in either an active state or an inactive state, the methods, devices, and systems can determine a linear number D of elements in the active state needed to achieve a total combined activity corresponding to a desired behavior, compare a number A of elements in an active state to the linear number D of elements needed to achieve the desired behavior, activate a first number n of inactive elements, and deactivate a second number m of active elements, wherein the difference between the first number n and the second number m is equal to the difference between the linear number D of elements needed to achieve the desired behavior and the present number A of elements in an active state.

Claims (49)

1. A method for operating an array of two-state elements that can be independently positioned in either an active state or an inactive state, the method comprising:

determining a linear number D of elements in the active state needed to achieve a total combined activity corresponding to a desired behavior;

comparing a number A of elements in an active state to the linear number D of elements needed to achieve the desired behavior; and

activating a first number n of inactive elements and deactivating a second number m of active elements, wherein the difference between the first number n and the second number m is equal to the difference between the linear number D of elements needed to achieve the desired behavior and the present number A of elements in an active state.

2. The method of claim 1 , wherein each of the two-state elements comprises a capacitor; and

wherein the desired behavior comprises a total desired capacitance.

3. The method of claim 1 , wherein determining a linear number D of elements needed to achieve the desired behavior comprises:

receiving an input corresponding to a desired behavior; and

determining a linear number D of elements need to achieve the total combined activity corresponding to the desired behavior.

4. The method of claim 3 , wherein the input comprises a binary input.

5. The method of claim 1 , wherein, when the present number A of elements in an active state is less than the linear number D of elements needed to achieve the desired behavior, activating a first number n of inactive elements comprises activating a number of inactive elements equal to the difference between the present number A of elements in an active state and the linear number D of elements needed to achieve the desired behavior, and deactivating a second number m of active elements comprises deactivating zero elements.

6. The method of claim 1 , wherein, when the present number A of elements in an active state is greater than the linear number of elements D needed to achieve the desired behavior, activating a first number n of inactive elements comprises activating zero elements, and deactivating a second number m of active elements comprises deactivating a number of active elements equal to the difference between the present number A of elements in an active state and the linear number D of elements needed to achieve the desired behavior.

7. The method of claim 1 , wherein n and m are both non-zero values.

8. The method of claim 7 , wherein, when the number of elements in an active state is equal to the linear number of elements needed to achieve the desired behavior, activating a first number n of inactive elements and deactivating a second number m of active elements comprises activating and deactivating an equal, non-zero number of inactive and active elements, respectively. (i.e. n=m).

9. The method of claim 1 , wherein activating a first number n of inactive elements comprises activating a plurality of elements that are spaced apart from each other within the array.

10. The method of claim 1 , wherein activating a first number n of inactive elements comprises activating one or more elements according to a predetermined sequential order of the elements in the array.

11. The method of claim 10 , wherein the predetermined sequential order is followed in a continuous, repeating pattern.

12. The method of claim 10 , wherein activating one or more elements according to a predetermined sequential order of the elements in the array comprises referencing a mapping table in which the predetermined sequential order is mapped to locations of the elements within the array.

13. The method of claim 12 , wherein the mapping table is one of a fixed or a programmable table.

14. The method of claim 12 , wherein referencing a mapping table comprises:

activating one or more elements starting at a first pointer that identifies an inactive element that is next to be activated according to the predetermined sequential order; and

advancing the first pointer by n positions in the predetermined sequential order.

15. The method of claim 14 , wherein referencing a mapping table comprises:

activating an inactive element identified by the first pointer;

advancing the first pointer by one position in the predetermined sequential order; and

repeating the steps of activating and advancing until n inactive elements have been activated.

16. The method of claim 10 , wherein the predetermined sequential order of the elements in the array is interleaved across the array.

17. The method of claim 1 , wherein deactivating a second number m of active elements comprises deactivating one or more elements according to a predetermined sequential order of the elements in the array.

18. The method of claim 17 , wherein the predetermined sequential order is followed in a continuous, repeating pattern.

19. The method of claim 17 , wherein deactivating one or more elements according to a predetermined sequential order of the elements in the array comprises referencing a mapping table in which the predetermined sequential order is mapped to locations of the elements within the array.

20. The method of claim 19 , wherein the mapping table is one of a fixed or a programmable table.

21. The method of claim 19 , wherein referencing a mapping table comprises:

deactivating one or more elements starting at a second pointer that identifies an active element that is next to be deactivated according to the predetermined sequential order; and

advancing the second pointer by m positions in the predetermined sequential order.

22. The method of claim 21 , wherein referencing a mapping table comprises:

deactivating one active element identified by the second pointer;

advancing the second pointer by one position in the predetermined sequential order; and

repeating the steps of deactivating and advancing until m active elements have been deactivated.

23. The method of claim 17 , wherein the predetermined sequential order of the elements in the array is interleaved across the array.

24. A system for switched capacitor array control comprising:

an array of two-state elements that can be independently positioned in either an active state or an inactive state; and

a controller configured to receive an input corresponding to a desired behavior, to determine a linear number D of the two-state elements in the active state needed to achieve a total combined activity corresponding to the desired behavior, to compare a number A of the elements in the active state to the linear number D of the elements needed to achieve the desired behavior, and to activate a first number n of inactive ones of the elements and deactivating a second number m of active ones of the elements, wherein the difference between the first number n and the second number m is equal to the difference between the linear number D of the elements needed to achieve the desired behavior and the present number A of the elements in an active state.

25. The system of claim 24 , wherein each of the two-state elements comprises a capacitor; and

wherein the desired behavior comprises a total desired capacitance.

26. The system of claim 24 , wherein each of the two-state elements is assigned a unique address.

27. The system of claim 26 , wherein the unique address comprises a unique binary identifier.

28. The system of claim 24 , wherein the array of two-state elements are arranged in one or more discrete banks each containing a subset of the two-state elements.

29. The system of claim 28 , wherein the two-state elements are each assigned a sequential number within one of the one or more discrete banks;

wherein the controller is configured to activate the first number n of inactive ones of the elements and deactivating the second number m of active ones of the elements in order of the sequential number of the two-state elements within the one of the one or more discrete banks.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2022
From: WISPRY, INC.
To: AAC TECHNOLOGIES PTE. LTD.
Reel/Frame 059096/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2014
From: MORRIS, ARTHUR S., III
To: WISPRY, INC.
Reel/Frame 032490/0038 →
Continuity (2)
Provisional Application 61671494 · Jul 13, 2012
Related Publication 20140015589A1 · Jan 16, 2014