Combined floating point multiplier adder with intermediate rounding logic

1. A method, comprising:

identifying, in a binary optimizer to execute on one or more hardware processor cores of a processor, a code region eligible for cumulative multiply add (CMA) optimization;

translating code region instructions into interpreter code instructions, including translating sequences of multiply add instructions in the code region instructions into fusion code comprising CMA instructions;

executing the interpreter code instructions, including executing the fusion code in a CMA arithmetic logic unit (ALU) of the processor;

monitoring floating point (FP) exceptions generated by the fusion code; and

retranslating at least a portion of the code region instructions to eliminate the fusion code from the portion of the code region responsive to receiving a number of CMA intermediate rounding exceptions exceeding a threshold.

2. The method of claim 1 , wherein the monitoring of FP exceptions generated by the fusion code includes:

responsive to receiving the FP exception, determining if the FP exception is one of the CMA intermediate rounding exceptions; and

responsive to determining that the FP exception is one of the CMA intermediate rounding exceptions:

determining if a CMA intermediate rounding exception corresponding to the FP exception is a first fault;

responsive to determining that the CMA intermediate rounding exception corresponding to the FP exception is a first fault, initializing a CMA region counter; and

responsive to determining that the CMA intermediate rounding exception corresponding to the FP exception is not a first fault:

incrementing the CMA region counter; and

determining if the CMA region counter has exceeded the threshold.

3. The method of claim 2 , further comprising:

responsive to determining that the FP exception is not one of the CMA intermediate rounding exceptions, performing an FP exception treatment.

4. The method of claim 2 , further comprising:

identifying multiple code regions eligible for CMA optimization;

generating interpreter code corresponding to each of the code regions;

assigning each of the code regions its own CMA region counter; and

retranslating individual code regions without fusion code based on their corresponding CMA region counter.

5. The method of claim 2 , further comprising:

periodically resetting the CMA region counter.

6. The method of claim 1 , wherein executing the interpreter code instructions includes executing a floating point multiply add sequence in a fused multiply add pipeline.

7. The method of claim 6 , wherein the fused multiply add pipeline includes CMA rounding logic at an output of a CMA multiplier.

8. The method of claim 2 , further comprising:

responsive to determining that the FP exception is one of the CMA intermediate rounding exceptions:

obtaining a faulting CMA instruction ID;

associating a CMA instruction counter with the CMA instruction ID;

counting the CMA intermediate rounding exceptions associated with the CMA instruction ID; and

responsive to determining that the CMA instruction counter has exceeded the threshold:

retranslating with selective fusion code; and

disabling the fusion code for a particular CMA instruction that caused the exception.

9. The method of claim 8 , wherein the CMA instruction counter is periodically reset.

10. The method of claim 8 , wherein a CMA rounding error is reported to a CMA intermediate rounding exception IP register.

11. The method of claim 10 , wherein the CMA intermediate rounding exception IP register is exposed to software using a read special register instruction.

12. A processor, comprising:

a level one (L1) instruction cache;

a front-end to fetch and decode instructions from the L1 instruction cache;

an L1 data cache; and

an execution pipeline to execute decoded instructions, wherein the execution pipeline includes a cumulative multiply add (CMA) arithmetic logic unit (ALU), including a multiplier and an adder and CMA rounding logic to report a first rounding exception generated by the multiplier.

13. The processor of claim 12 , further comprising:

a register to store an address of an instruction responsive to generation of a CMA rounding error exception.

14. The processor of claim 12 , wherein the CMA ALU includes fused multiply add (FMA) rounding logic to report a second rounding exception generated by the adder.

15. The processor of claim 14 , further comprising:

logic to generate a floating point exception signal based on the first rounding exception.

16. The processor of claim 15 , further comprising:

logic to generate a floating point exception signal based on the second rounding exception.

17. A computer system, comprising:

a processor comprising:

a level one (L1) instruction cache;

a front-end to fetch and decode instructions from the L1 instruction cache;

an L1 data cache; and

an execution pipeline to execute decoded instructions, wherein the execution pipeline includes a cumulative multiply add (CMA) arithmetic logic unit (ALU), including a multiplier and an adder and CMA rounding logic to report a first rounding exception generated by the multiplier; and

storage accessible to the processor; wherein the storage includes processor executable code to cause the processor to perform operations comprising:

identifying a code region eligible for CMA optimization;

translating code region instructions into interpreter code instructions, including translating sequences of multiply add instructions in the code region instructions into fusion code comprising CMA instructions;

executing the interpreter code instructions, including executing the fusion code;

monitoring floating point (FP) exceptions generated by the fusion code; and

retranslating at least a portion of the code region instructions to eliminate the fusion code from the portion of the code region responsive to receiving a number of CMA intermediate rounding exceptions exceeding a threshold.

18. The system of claim 17 , wherein the monitoring of FP exceptions generated by the fusion code includes:

responsive to receiving the FP exception, determining if the FP exception is one of the CMA intermediate rounding exceptions; and

responsive to determining that the FP exception is one of the CMA intermediate rounding exceptions:

determining if a CMA intermediate rounding exception corresponding to the FP exception is a first fault;

responsive to determining that the CMA intermediate rounding exception corresponding to the FP exception is a first fault, initializing a CMA region counter; and

responsive to determining that the CMA intermediate rounding exception corresponding to the FP exception is not a first fault:

incrementing the CMA region counter; and

determining if the CMA region counter has exceeded the threshold.

19. The system of claim 18 , wherein the storage further includes processor executable code to cause the processor to perform operations comprising:

responsive to determining that the FP exception is not one of the CMA intermediate rounding exceptions, performing an FP exception treatment.

20. The system of claim 18 , wherein the storage further includes processor executable code to cause the processor to perform operations comprising:

identifying multiple code regions eligible for CMA optimization;

generating interpreter code corresponding to each of the code regions;

assigning each of the code regions its own CMA region counter; and

retranslating individual code regions without fusion code based on their corresponding CMA region counter.

21. The system of claim 18 , wherein the storage further includes processor executable code to cause the processor to perform operations comprising:

periodically resetting the CMA region counter.

22. The system of claim 17 , wherein executing the interpreter code instructions includes executing a floating point multiply add sequence in a fused multiply add pipeline.

23. The system of claim 22 , wherein the fused multiply add pipeline includes CMA rounding logic at an output of the multiplier.

24. The system of claim 18 , wherein the storage further includes processor executable code to cause the processor to perform operations comprising:

responsive to determining that the FP exception is one of the CMA intermediate rounding exceptions:

obtaining a faulting CMA instruction ID;

associating a CMA instruction counter with the CMA instruction ID;

counting the CMA intermediate rounding exceptions associated with the CMA instruction ID; and

responsive to determining that the CMA instruction counter has exceeded the threshold:

retranslating with selective fusion code; and

disabling the fusion code for a particular CMA instruction that caused the exception.

25. The system of claim 24 , wherein the CMA instruction counter is to be periodically reset.

26. The system of claim 24 , wherein a CMA rounding error is to be reported to a CMA intermediate rounding exception IP register.

27. The system of claim 26 , wherein the CMA intermediate rounding exception IP register is to be exposed to software using a read special register instruction.

28. A non-transitory computer readable storage medium including processor-executable instructions to cause a processor to perform operations comprising:

identifying a code region eligible for cumulative multiply add (CMA) optimization;

translating code region instructions into interpreter code instructions, including translating sequences of multiply add instructions in the code region instructions into fusion code comprising CMA instructions;

executing the interpreter code instructions, including executing the fusion code;

monitoring floating point (FP) exceptions generated by the fusion code; and

retranslating at least a portion of the code region instructions to eliminate the fusion code from the portion of the code region responsive to receiving a number of CMA intermediate rounding exceptions exceeding a threshold.

29. The non-transitory computer readable storage medium of claim 28 , wherein the monitoring of FP exceptions generated by the fusion code includes:

responsive to receiving the FP exception, determining if the FP exception is one of the CMA intermediate rounding exceptions; and

responsive to determining that the FP exception is one of the CMA intermediate rounding exceptions:

determining if a CMA intermediate rounding exception corresponding to the FP exception is a first fault;

responsive to determining that the CMA intermediate rounding exception corresponding to the FP exception is a first fault, initializing a CMA region counter; and

responsive to determining that the CMA intermediate rounding exception corresponding to the FP exception is not a first fault:

incrementing the CMA region counter; and

determining if the CMA region counter has exceeded the threshold.

30. The non-transitory computer readable storage medium of claim 29 , wherein the operations include further operations for:

responsive to determining that the FP exception is not one of the CMA intermediate rounding exceptions, performing an FP exception treatment.