Integrated circuit system with non-volatile memory stress suppression and method of manufacture thereof
View Patent ↗An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line.
1. A method of manufacturing an integrated circuit system comprising:
providing an integrated circuit die;
forming a non-volatile memory cell in the integrated circuit die and a bit line for reading a data condition state of the non-volatile memory cell; and
forming a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected at a first end to the bit line and at a second end to a voltage limiter, wherein the semiconductor switch is for reducing voltage excursions on the bit line, wherein the voltage clamp limits voltages on the bit line to a predetermined threshold level when the non-volatile memory cell is in a high resistive state, wherein the semiconductor switch enables the voltage clamp only during memory read operations and disables the voltage clamp during memory write operations, and wherein forming the voltage limiter of the voltage clamp includes: forming a semiconductor current sink having a first end connected to the semiconductor switch and having a second end connected to ground, wherein the semiconductor switch is between the bit line and the semiconductor current sink, and forming an operational amplifier, wherein an output of the operational amplifier is connected to a gate of a transistor provided as part of the semiconductor current sink.
2. A method of manufacturing an integrated circuit system comprising:
providing an integrated circuit die;
forming a non-volatile memory cell in the integrated circuit die and a bit line for reading a data condition state of the non-volatile memory cell; and
forming a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected at a first end to the bit line and at a second end to a voltage limiter, wherein the semiconductor switch is for reducing voltage excursions on the bit line, wherein the voltage clamp limits voltages on the bit line to a predetermined threshold level when the non-volatile memory cell is in a high resistive state, wherein the semiconductor switch enables the voltage clamp only during memory read operations and disables the voltage clamp during memory write operations, wherein forming the voltage clamp includes forming a resistive compensation device connected directly to the second end of the semiconductor switch, wherein the first end of the semiconductor switch is connected directly to the bit line, and wherein the resistive compensation device is a thermal sensitive resistor.
3. An integrated circuit system comprising:
an integrated circuit die;
a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell;
a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line, wherein the voltage clamp limits voltages on the bit line to a predetermined threshold level when the non-volatile memory cell is in a high resistive state, wherein the semiconductor switch enables the voltage clamp only during memory read operations and disables the voltage clamp during memory write operations;
a resistive compensation device connected directly to a second end of the semiconductor switch, wherein a first end of the semiconductor switch is connected directly to the bit line, and wherein the resistive compensation device is a thermal sensitive resistor.
4. An integrated circuit system comprising:
an integrated circuit die;
a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell;
a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line, wherein the voltage clamp limits voltages on the bit line to a predetermined threshold level when the non-volatile memory cell is in a high resistive state, wherein the semiconductor switch enables the voltage clamp only during memory read operations and disables the voltage clamp during memory write operations;
a semiconductor current sink connected between the semiconductor switch and ground; and
an operational amplifier connected to the semiconductor current sink, wherein an output of the operational amplifier is connected to a gate of a transistor provided as part of the semiconductor current sink.
5. The method as claimed in claim 1 , wherein a non-inverting input of the operational amplifier is connected to the second end of the semiconductor switch.
6. The method as claimed in claim 5 , wherein an inverting input of the operational amplifier is connected to a reference voltage.
7. The system as claimed in claim 4 , wherein a non-inverting input of the operational amplifier is connected to an output of the semiconductor switch.
8. The system as claimed in claim 7 , wherein an inverting input of the operational amplifier is connected to a reference voltage.