Stack packages having token ring loops
Stack packages are provided. The stack package includes a substrate having first and second bond fingers and a plurality of semiconductor chips stacked on the substrate. Each of the plurality of semiconductor chips has an input bonding pad and an output bonding pad. A first interconnection electrically connects the first bond finger to the input bonding pad of a lowermost semiconductor chip of the plurality of semiconductor chips. A second interconnection electrically connects the output bonding pad of a lower semiconductor chip of the plurality of semiconductor chips to the input bonding pad of an upper semiconductor chip stacked on the lower semiconductor chip. A third interconnection electrically connects the output bonding pad of an uppermost semiconductor chip of the plurality of semiconductor chips to the second bond finger.
1. A stack package comprising:
a substrate having a first bond finger and a second bond finger;
a plurality of semiconductor chips stacked on the substrate, each of the plurality of semiconductor chips having an input bonding pad and an output bonding pad;
a first interconnection electrically connecting the first bond finger to the input bonding pad of a lowermost semiconductor chip of the plurality of semiconductor chips;
a second interconnection electrically connecting the output bonding pad of a lower semiconductor chip of the plurality of semiconductor chips to the input bonding pad of an upper semiconductor chip stacked on the lower semiconductor chip; and
a third interconnection electrically connecting the output bonding pad of an uppermost semiconductor chip of the plurality of semiconductor chips to the second bond finger.
2. The stack package of claim 1 , wherein the plurality of semiconductor chips are stacked to have a step structure to expose the input bonding pads and the output bonding pads.
3. The stack package of claim 1 , wherein each of the first to third interconnections includes a metal wire.
4. The stack package of claim 1 , wherein the first and second bond fingers act as an input terminal and an output terminal, respectively.
5. The stack package of claim 1 , wherein the input bonding pad and the output bonding pad of each of the semiconductor chips are connected to each other through an internal circuit integrated in the corresponding semiconductor chip.
6. A stack package comprising:
a substrate having a first bond finger and a second bond finger;
a plurality of semiconductor chips stacked on the substrate, each of the plurality of semiconductor chips having an input bonding pad, an output bonding pad and a dummy pad;
a first interconnection electrically connecting the first bond finger to the input bonding pad of a lowermost semiconductor chip of the plurality of semiconductor chips;
a second interconnection electrically connecting the output bonding pad of a lower semiconductor chip of the plurality of semiconductor chips to the input bonding pad of an upper semiconductor chip stacked on the lower semiconductor chip;
a third interconnection electrically connecting the output bonding pad of an upper semiconductor chip of the plurality of semiconductor chips to the dummy pad of a lower semiconductor chip under the upper semiconductor chip; and
a fourth interconnection electrically connecting the dummy pad of a lowermost semiconductor chip of the plurality of semiconductor chips to the second bond finger.
7. The stack package of claim 6 , wherein the plurality of semiconductor chips are stacked to have a step structure to expose the input bonding pads, the output bonding pads, and the dummy pads.
8. The stack package of claim 6 , wherein the first and second bond fingers act as an input terminal and an output terminal, respectively.
9. The stack package of claim 6 , wherein the input bonding pad and the output bonding pad of each of the semiconductor chips are connected to each other through an internal circuit integrated in the corresponding semiconductor chip.