Error correction code for unidirectional memory
A memory array and a method of writing to a unidirectional non-volatile storage cell are disclosed whereby a user data word is transformed to an internal data word and written to one or more unidirectional data storage cells according to a cell coding scheme. A check word may be generated that corresponds to the internal data word. In some embodiments, the check word may be generated by inverting one or more bits of an intermediate check word. Other embodiments may be described and claimed.
1. A method of providing error correction, the method comprising:
computing a first check code for first data, wherein the first check code corresponds to a first matrix multiplication of the first data and a matrix;
selectively inverting bits of the first check code to generate a second check code according to an inversion pattern, wherein the inversion pattern corresponds to a second matrix multiplication of an initial data comprising erased states and the matrix; and
programming the first data and the second check code to a plurality of data storage cells.
2. The method of claim 1 , further comprising:
receiving user data; and
transforming the user data to the first data according to a transformation function, the first data being the same size as the user data.
3. The method of claim 2 , wherein transforming further comprises transforming according to a Gray code.
4. The method of claim 1 , wherein the data storage cells comprise unidirectional non-volatile data storage cells.
5. The method of claim 1 , wherein the data storage cells comprise flash memory cells.
6. The method of claim 1 , wherein the inversion pattern comprises a plurality of bits having a first state or a second state, wherein selectively inverting comprises inverting bits of the first check code corresponding to bit positions of the inversion pattern having the first state and not inverting bit positions corresponding to the second state.
7. The method of claim 1 , wherein the matrix comprises:
[
0010
1011
1111
1110
1011
0010
0001
1101
1110
1000
0100
1111
1101
1011
0111
0111
]
.
8. An apparatus comprising:
a controller configured to:
compute a first check code for first data, wherein the first check code corresponds to a first matrix multiplication of the first data and a matrix;
selectively invert bits of the first check code to generate a second check code according to an inversion pattern, wherein the inversion pattern corresponds to a second matrix multiplication of an initial data comprising erased states and the matrix; and
program the first data and the second check code to a plurality of data storage cells.
9. The apparatus of claim 8 , wherein the controller is further configured to:
receive user data; and
transform the user data to the first data according to a transformation function, the first data being the same size as the user data.
10. The apparatus of claim 9 , wherein the controller is further configured to transform the user data according to a Gray code.
11. The apparatus of claim 8 , wherein the data storage cells comprise unidirectional non-volatile data storage cells.
12. The apparatus of claim 8 , wherein the data storage cells comprise flash memory cells.
13. The apparatus of claim 8 , wherein the inversion pattern comprises a plurality of bits having a first state or a second state, wherein the controller is configured to selectively invert bits of the first check code corresponding to bit positions of the inversion pattern having the first state and not invert bit positions corresponding to the second state.
14. The apparatus of claim 8 , wherein the matrix comprises:
[
0010
1011
1111
1110
1011
0010
0001
1101
1110
1000
0100
1111
1101
1011
0111
0111
]
.
15. A memory system comprising:
a plurality of data storage cells; and
a controller configured to:
compute a first check code for first data, wherein the first check code corresponds to a first matrix multiplication of the first data and a matrix;
selectively invert bits of the first check code to generate a second check code according to an inversion pattern, wherein the inversion pattern corresponds to a second matrix multiplication of an initial data comprising erased states and the matrix; and
program the first data and the second check code to the plurality of data storage cells.
16. The memory system of claim 15 , wherein the controller is further configured to:
receive user data; and
transform the user data to the first data according to a transformation function, the first data being the same size as the user data.
17. The memory system of claim 16 , wherein the controller is further configured to transform the user data according to a Gray code.
18. The memory system of claim 15 , wherein the data storage cells comprise flash memory cells.
19. The memory system of claim 15 , wherein the inversion pattern comprises a plurality of bits having a first state or a second state, wherein the controller is configured to selectively invert bits of the first check code corresponding to bit positions of the inversion pattern having the first state and not invert bit positions corresponding to the second state.
20. The memory system of claim 15 , wherein the matrix comprises:
[
0010
1011
1111
1110
1011
0010
0001
1101
1110
1000
0100
1111
1101
1011
0111
0111
]