Advanced memory interfaces and methods
Controllers, interfaces, memory devices, methods and systems are disclosed, including a controller configured to interface with a separate memory device and perform an iterative write operation to program a selected memory cell of the memory device to a target state, wherein each iteration of the write operation is configured to successively change a physical state of the selected memory cell. Other controllers, interfaces, memory device, methods and systems are also described, such as those where either a controller or a memory device can throttle a data communication operation, and/or those that utilize customized programming pulses.
1. A controller configured to interface with a separate memory device and perform an iterative write operation to program a selected memory cell of the memory device to a target state, wherein each iteration of the write operation is configured to successively change a physical state of the selected memory cell and the controller is configured to interface with the memory device over a serial communication interface including a sync handshake line and wherein the controller is configured to throttle each iteration of the write operation by signaling on the sync handshake line.
2. The controller of claim 1 , wherein the controller is configured to determine the physical state of the selected memory cell after an iteration of the write operation and configure a next iteration of the write operation responsive to the determined physical state of the selected memory cell.
3. The controller of claim 2 , wherein the controller being configured to configure the next iteration of the write operation comprises the controller being configured to configure a next programming pulse.
4. The controller of claim 1 , wherein the iterative write operation comprises a fixed number of iterations.
5. The controller of claim 1 , wherein the controller is further configured to compare the physical state of the selected memory cell to the target state.
6. The controller of claim 1 wherein each iteration of the write operation is configured to incrementally change a physical value.
7. The controller of claim 6 wherein each iteration of the write operation is configured to increment the physical value by an at least approximately equal amount.
8. The controller of claim 7 wherein the controller is configured to increment the physical value until the physical value is within a particular range associated with the target state.
9. The controller of claim 7 wherein the controller is configured to read back the physical value after each iteration of the write operation.
10. The controller of claim 1 wherein the controller is configured to establish two or more levels of the physical value in each memory cell of the nonvolatile memory.
11. The controller of claim 1 wherein each iteration of the write operation is configured to cause charge to be stored in the selected memory cell.
12. The controller of claim 11 wherein the iterative write operation is configured to successively increase a magnitude of the charge stored in the selected memory cell until the charge magnitude is within a particular range associated with the target state.
13. The controller of claim 12 , wherein the controller is configured to interface with a plurality of memory devices.
14. The controller of claim 1 wherein the controller is configured to interface with the memory device using a digital interface.
15. The controller of claim 1 wherein the controller is configured to interface with the memory device using an analog interface.
16. The controller of claim 1 wherein the controller includes a processing arrangement that is configured to control the iterative write operation.
17. The controller of claim 16 , wherein the processing arrangement includes an iterate engine.
18. The controller of claim 17 , wherein the processing arrangement further includes a processor in communication with the iterate engine.
19. The controller of claim 16 , wherein the processing arrangement includes a processor.
20. The controller of claim 1 wherein the selected memory cell is one memory cell of a page of memory cells and the iterative write operation is configured to program each memory cell of the page of memory cells substantially simultaneously.
21. The controller of claim 20 wherein the page of memory cells is one page of a plurality of pages of memory cells, and the controller is configured to program each page of the plurality of pages successively.
22. The controller of claim 21 wherein each page of the plurality of memory pages is sequentially addressable and the controller is configured to increment an initial page address to access sequential ones of the plurality of memory pages.
23. The controller of claim 1 , wherein the controller is configured to interface with the memory device using, at least in part, a serial communication interface.
24. The controller of claim 23 wherein the controller is configured to communicate a clear iterate bit on the serial communication interface to indicate completion of the iterative write operation.
25. The controller of claim 1 , wherein signaling on the sync handshake line by the controller throttles a read operation.
26. The controller of claim 1 , further comprising:
a synchronous handshake section to provide a drive signal; and
a pulse unit digital to analog converter configured to provide a programming pulse responsive to received write data and the drive signal, wherein the programming pulse has a pulse shape configured responsive to the target state of the selected memory cell.
27. In a controller that is configured to interface with a separate memory device, a method comprising:
performing an iterative write operation to program a selected memory cell of the memory device to a target state, wherein each iteration of the write operation is configured to successively change a physical state of the selected memory cell; and
interfacing with the memory device over a serial communication interface including a sync handshake line to throttle each iteration of the write operation by signaling on the sync handshake line.