Integrated circuits and methods for processing integrated circuits with embedded features
View Patent ↗Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect, within a substrate, such as an interlayer dielectric substrate, includes providing a substrate having an embedded copper feature disposed therein. The embedded copper feature has an exposed surface and the substrate has a substrate surface adjacent to the exposed surface of the embedded copper feature. The exposed surface of the embedded copper feature is nitrided to form a layer of copper nitride in the embedded copper feature. Copper nitride is selectively etched from the embedded copper feature to recess the embedded copper feature within the substrate.
1. An integrated circuit comprising:
a semiconductor substrate;
an interlayer dielectric substrate disposed on the semiconductor substrate, the interlayer dielectric substrate having an embedded copper interconnect disposed therein, the embedded copper interconnect recessed in the interlayer dielectric substrate and defining a recessed surface;
wherein a recessed surface of the embedded copper interconnect has an average surface roughness R a of less than or equal to about 20 nm.
2. The integrated circuit of claim 1 , wherein the average surface roughness of the recessed surface is less than or equal to about 5 nm.
3. The integrated circuit of claim 1 , wherein the average surface roughness of the recessed surface is from about 0.1 to about 5 nm.
4. The integrated circuit of claim 1 , further comprising a capping layer disposed over the embedded copper interconnect and in contact with the recessed surface of the embedded copper interconnect.
5. The integrated circuit of claim 4 , further comprising another interlayer dielectric substrate disposed on the capping layer, wherein the other interlayer dielectric substrate has an embedded copper interconnect disposed therein.
6. The integrated circuit of claim 1 , wherein the interlayer dielectric substrate comprises a plurality of individual dielectric layers.
7. The integrated circuit of claim 6 , wherein the plurality of individual dielectric layers includes a low k or ultra-low k layer and a tetraethylorthosilicate layer disposed thereon.
8. The integrated circuit of claim 6 , wherein the embedded copper feature at least partially extends into one or more of the plurality of individual dielectric layers of the interlayer dielectric substrate substrate.
9. The integrated circuit of claim 1 , wherein the embedded copper feature extends completely through the interlayer dielectric substrate.
10. The integrated circuit of claim 1 , wherein the interlayer dielectric substrate comprises a plurality of embedded copper features disposed therein.
11. The integrate circuit of claim 10 , wherein some of the embedded copper features in the interlayer dielectric substrate are unrecessed.
12. An integrated circuit comprising:
a semiconductor substrate;
an interlayer dielectric substrate disposed on the semiconductor substrate and comprising a plurality of individual dielectric layers, wherein the interlayer dielectric substrate comprises a plurality of embedded copper interconnects disposed in and at least partially extending into one or more of the plurality of individual dielectric layers of the interlayer dielectric substrate, and wherein at least some of the embedded copper interconnect are recessed in the interlayer dielectric substrate and define a recessed surface;
a capping layer disposed over the embedded copper interconnect and in contact with the recessed surface of the embedded copper interconnect;
another interlayer dielectric substrate disposed on the capping layer;
wherein a recessed surface of the embedded copper interconnects has an average surface roughness R a of less than or equal to about 20 nm.