Methods for fabricating a metal structure for a semiconductor device
View Patent ↗A method for fabricating a metal structure for a semiconductor device is disclosed. The method begins with providing a wafer with a current input contact and current output contact. Remaining steps include loading the wafer into a deposition apparatus, depositing a layer of metal onto a predefined metal region, removing the wafer from the deposition apparatus, and performing an ex-situ passivation process. If additional layers are to be deposited and passivated, the steps are repeated until a predetermined number of layers of metal are deposited onto the predefined metal region. The predefined metal region is a gate metal opening if the metal structure is a gate contact for a field effect transistor. The ex-situ passivation process is achievable through oxidation or nitridation of the wafer using either oxygen plasma or a nitrogen plasma, respectively. Alternately, oxidation is also achievable through exposing the wafer to air at an elevated temperature.
1. A method for fabricating a metal structure for a field effect device (FED) comprising:
providing the FED with a gate recess over a substrate;
forming a gate comprising the steps of:
subjecting the FED to a vacuum;
depositing under the vacuum a first metal layer extending into and covering a bottom portion of the gate recess, wherein the first metal layer is formed from a metal selected from a group consisting of nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), and aluminum (Al);
removing the FED from the vacuum;
forming a first passivation layer by oxidizing a top surface of the first metal layer, wherein oxidizing the top surface of the first metal layer is accomplished by exposure to oxygen plasma while the FED is ex-situ and not under vacuum;
subjecting the FED to the vacuum;
depositing under vacuum a second metal layer over the first passivation layer, wherein the second metal layer is formed from a metal selected from a group consisting of nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), and aluminum (Al); and
depositing under vacuum a current carrying layer over the second metal layer.
2. The method of claim 1 wherein the first metal layer forms a Schottky metal contact region.
3. The method of claim 1 wherein the current carrying layer is formed from a noble metal.
4. The method of claim 1 further including depositing additional metal layers formed from metals selected from a group consisting of nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), and aluminum (Al) prior to depositing the current carrying layer.
5. The method of claim 1 further including performing a liftoff of unwanted metal.
6. The method of claim 1 further including:
defining a gate metal pattern; and
etching a gate metal structure using the gate metal pattern.
7. The method of claim 1 wherein each of the first metal layer and the second metal layer is deposited with a thickness that ranges from around about 30 Angstroms to less than 49 Angstroms.
8. The method of claim 1 wherein the FED is a gallium nitride (GaN) high electron mobility transistor (HEMT).
9. The method of claim 1 wherein the FED is a metal semiconductor field effect transistor (MESFET).
10. The method of claim 1 wherein the FED is a heterostructure field effect transistor (HFET).
11. The method of claim 1 further including adding a second passivation layer over the second metal layer.