IP Library Patent Application 13853106
Patent Application
App. No. 13/853,106

METHOD OF CALCULATING CPU UTILIZATION

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Quick Facts
Patent No.
US None
App. No.
13/853,106
Abstract

A method of determining processor utilization includes: counting, via a first counter on a processor, a number of elapsed clock cycles while code is being executed; counting, via a second counter on a processor, a total number of free-running clock cycles; and dividing the number of clock cycles where code is being executed by the total number of free-running clock cycles to determine a CPU utilization.

Claims (58)

1 . A method of determining processor utilization comprising:

counting, via a first counter on a processor, a number of elapsed clock cycles while code is being executed;

counting, via a second counter on the processor, a total number of free-running clock cycles;

dividing the number of clock cycles where code is being executed by the total number of free-running clock cycles to determine a CPU utilization;

wherein counting the number of elapsed clock cycles where code is being executed includes:

initializing the first counter to a predetermined value;

detecting, via hardware, the start of an interrupt service routine;

unfreezing the first counter to allow the counter to begin incrementing clock cycles;

detecting, via hardware, the completion of the interrupt service routine;

freezing the first counter to prevent the counter from further incrementing; and

determining the number of clock cycles that have elapsed since the first counter was initialized.

2 . The method of claim 1 , wherein the first counter is stored in a first register; and wherein the second counter is stored in a second register.

3 . The method of claim 2 , wherein the processor includes an instruction execution unit configured for software code execution, and a performance monitor unit;

wherein the performance monitor unit is configured to operate separate from the instruction execution unit; and

wherein the first counter is stored in a register maintained by the performance monitor unit.

4 . The method of claim 1 , wherein the processor includes an instruction execution unit configured for software code execution, and a performance monitor unit;

wherein the performance monitor unit is configured to operate separate from the instruction execution unit; and

wherein the first counter is stored in a register maintained by the performance monitor unit.

5 . The method of claim 4 , wherein detecting, via hardware, the start of an interrupt service routine is performed by the performance monitor unit.

6 . The method of claim 1 , wherein detecting, via hardware, the start of an interrupt service routine includes detecting the start of any interrupt service routine.

7 . The method of claim 1 , wherein detecting, via hardware, the start of an interrupt service routine includes detecting the start of a specific interrupt service routine.

8 . The method of claim 1 , further comprising resetting each of the first and second counters on a periodic basis.

9 . The method of claim 1 , further comprising freezing the first counter if the processor is in a background idle state.

10 . A method of determining processor utilization comprising:

counting, via a first counter on a processor, a number of elapsed clock cycles while code is being executed;

determining a CPU utilization from the number of elapsed clock cycles while code is being executed;

wherein the processor includes an instruction execution unit configured for software code execution, and a performance monitor unit;

wherein the performance monitor unit is configured to operate separate from the instruction execution unit;

wherein the first counter is stored in a register maintained by the performance monitor unit; and

wherein counting the number of elapsed clock cycles where code is being executed includes:

initializing the first counter to a predetermined value;

detecting, via hardware, the start of an interrupt service routine;

unfreezing the first counter to allow the counter to begin incrementing clock cycles;

detecting, via hardware, the completion of the interrupt service routine;

freezing the first counter to prevent the counter from further incrementing; and

determining the number of clock cycles that have elapsed since the first counter was initialized.

11 . The method of claim 10 , wherein detecting, via hardware, the start of an interrupt service routine is performed by the performance monitor unit.

12 . The method of claim 10 , further comprising:

counting, via a second counter on a processor, a total number of free-running clock cycles; and

wherein determining a CPU utilization from the number of elapsed clock cycles while code is being executed includes dividing the number of clock cycles where code is being executed by the total number of free-running clock cycles to determine a CPU utilization.

13 . The method of claim 10 , wherein detecting, via hardware, the start of an interrupt service routine includes detecting the start of a specific interrupt service routine.

14 . The method of claim 10 , further comprising resetting each of the first and second counters on a periodic basis.

15 . The method of claim 10 , further comprising freezing the first counter if the instruction execution unit is in a background idle state.

16 . A method of determining processor utilization comprising:

counting, via a counter on a processor, a number of elapsed clock cycles while code is being executed;

initiating a first interrupt service routine having a fixed execution period;

multiplying, within the interrupt service routine, the number of clock cycles where code is being executed by a constant to determine a processor utilization percentage; and

wherein the constant is equal to the inverse of the fixed execution period multiplied by a clock speed of the processor.

17 . The method of claim 16 , wherein the processor includes an instruction execution unit configured for software code execution, and a performance monitor unit;

wherein the performance monitor unit is configured to operate separate from the instruction execution unit; and

wherein the counter is stored in a register maintained by the performance monitor unit.

18 . The method of claim 16 , wherein counting the number of elapsed clock cycles where code is being executed includes:

initializing the counter to a predetermined value;

detecting, via hardware, the start of a second interrupt service routine;

unfreezing the counter to allow the counter to begin incrementing clock cycles;

detecting, via hardware, the completion of the interrupt service routine;

freezing the counter to prevent the counter from further incrementing; and

determining the number of clock cycles that have elapsed since the counter was initialized.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2014
From: WILMINGTON TRUST COMPANY
To: GM GLOBAL TECHNOLOGY OPERATIONS LLC
Reel/Frame 034287/0601 →
SECURITY INTEREST Recorded Jun 12, 2014
From: GM GLOBAL TECHNOLOGY OPERATIONS LLC
To: WILMINGTON TRUST COMPANY
Reel/Frame 033135/0336 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2013
From: MURRELL, TERRY; RANSOM, RAY M.; KUMARA, NAMAL P.
To: GM GLOBAL TECHNOLOGY OPERATIONS LLC
Reel/Frame 030113/0390 →