IP Library Patent Application 13854140
Patent Application
App. No. 13/854,140

SEMICONDUCTOR DEVICE AND METHOD OF ASSEMBLING SAME

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Quick Facts
Patent No.
US None
App. No.
13/854,140
Abstract

A method of assembling a semiconductor device includes providing a lead frame having a die pad and a fame member with lead fingers that surround the die pad. The lead fingers have distal ends connected to the frame member and proximal ends near the die pad. A die is attached to the die pad and die connection pads are electrically connected to the proximal ends of the lead fingers with bond wires. The die, bond wires, and part of the lead fingers are encapsulated with an encapsulant. The encapsulating process includes separating the lead fingers into first and second sets of lead fingers. The proximal ends of the first set lie in a first plane and the proximal ends of the second set lie in a second plane that is spaced and maintained from the first plane solely by the encapsulation material.

Claims (29)

1 . A method of packaging a semiconductor die, the method comprising:

providing an electrically conductive lead frame sheet having at least one die pad, a frame member surrounding the die pad, and a plurality of lead fingers, wherein the lead fingers extend from the frame member towards the die pad, and wherein the lead fingers each have a distal end connected to the frame member and a proximal end near the die pad;

attaching a semiconductor die to the die pad;

electrically connecting contact pads on the semiconductor die with respective proximal ends of the lead fingers; and

encapsulating at least the die, the die pad and the proximal ends of the lead fingers with an encapsulation material, wherein the encapsulating includes separating the lead fingers into first and second sets of lead fingers, and wherein the proximal ends of the first set of lead fingers lie in a first plane and the proximal ends of the second set of lead fingers lie in a second plane that is spaced and maintained from the first plane solely by the encapsulation material.

2 . The method of packaging a semiconductor die of claim 1 , wherein the first and second sets of lead fingers are interleaved.

3 . The method of packaging a semiconductor die of claim 2 , wherein members of the first set of lead fingers are in an alternating arrangement with members of the second set of lead fingers.

4 . The method of packaging a semiconductor die of claim 1 , wherein the encapsulating is performed by molding.

5 . The method of packaging a semiconductor die of claim 4 , wherein the molding is performed by a mold within which the proximal ends of the lead fingers are seated, and wherein the mold has slots and anvils that capture and bend the proximal ends of the second set of lead fingers so that the proximal ends of the second set of lead fingers lie in the second plane.

6 . The method of packaging a semiconductor die of claim 1 , further comprising separating the lead fingers from the frame member.

7 . The method of packaging a semiconductor die of claim 6 , further comprising bending the lead fingers so that the distal ends of the lead fingers lie in a third plane that is spaced from the first and second planes.

8 . The method of packaging a semiconductor die of claim 7 , wherein the first and second planes are parallel to each other.

9 . The method of packaging a semiconductor die of claim 8 , wherein the third plane is parallel to the first plane.

10 . The method of packaging a semiconductor die of claim 1 , wherein each member of the second set of lead fingers is longer than each member of the first set of lead fingers.

11 . The method of packaging a semiconductor die of claim 1 , wherein the distal ends the second set of lead fingers are spaced further away from the encapsulation material than the distal ends of the first set of lead fingers.

12 . A semiconductor device, comprising:

a die pad;

a first set of lead fingers that are spaced from and project outwardly from the die pad, wherein the lead fingers have proximal ends close to the die pad and distal ends farther from the die pad, and wherein the proximal ends of the first set of lead fingers lie in a first plane;

a second set of lead fingers that are spaced from and project outwardly from the die pad, wherein the second set of lead fingers have proximal ends close to the die pad and distal ends farther from the die pad, and wherein the proximal ends of the second set of lead fingers lie in a second plane that is spaced from the first plane;

a semiconductor die attached to the die pad, wherein bonding pads on the semiconductor die are electrically coupled to respective said proximal ends of the first and second sets of lead fingers with bond wires; and

an encapsulation material covering the bond wires, semiconductor die and the proximal ends of the first and second sets of lead fingers, wherein the encapsulation material is disposed in a space between the proximal ends of the first and second sets of lead fingers such that the encapsulation material maintains the first set of lead fingers in the first plane and the second set of lead fingers in the second plane, and wherein the distal ends of the first and second sets of lead fingers project outwardly from the encapsulation material and allow for external electrical connection with the semiconductor die.

13 . The semiconductor device of claim 12 , wherein the first and second sets of lead fingers are interleaved.

14 . The semiconductor device of claim 13 , wherein members of the first set of lead fingers are in an alternating arrangement with members of the second set of lead fingers.

15 . The semiconductor device of claim 12 , wherein the encapsulation material is a molding compound and wherein the proximal ends of the second set of lead fingers were positioned to lie in the second plane when the lead fingers are covered with the encapsulation material.

16 . The semiconductor device of claim 12 , wherein the first and second planes are parallel to each other.

17 . The semiconductor device of claim 12 , wherein the distal ends of the lead fingers lie in a third plane that is spaced from the first and second planes.

18 . The semiconductor device of claim 17 , wherein the third plane is parallel to the first plane.

19 . The semiconductor device of claim 18 , wherein the third plane is parallel to the first and second planes.

20 . The semiconductor device of claim 12 , wherein the distal ends of the second set of lead fingers extend further away from the encapsulation material than the distal ends of the first set of lead fingers.

Assignments (18)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0804 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0844 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0819 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0510 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 031248/0750 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0627 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2013
From: YAO, JINZHONG; BAI, ZHIGANG; ZANG, YUAN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030120/0086 →