Patent Assignment
Reel/Frame 031248/0510
Supplement to Ip Security Agreement
Recorded: 2013-09-20
Pages: 17
Assignor
FREESCALE SEMICONDUCTOR, INC.
Executed: 2013-07-31
Assignee
CITIBANK, N.A., AS NOTES COLLATERAL AGENT
390 GREENWICH STREET, NEW YORK, NEW YORK, 10013
Covered Properties
(127)
Semiconductor Device and Method of Assembling Same
Semiconductor Device and Method of Assembling Same
Application:
13/854,140 →
Publication:
US US20130249071A1
Stiffened Semiconductor Die Package
Patent:
8,772,913 →
Application:
13/857,131 →
Method of Forming Stacked Die Package Using Redistributed Chip Packaging
Patent:
8,669,140 →
Application:
13/857,143 →
Methods and Apparatus for Calibrating Transducer-Including Devices
Double Patterning Aware Routing Without Stitching
Patent:
8,762,898 →
Application:
13/861,509 →
Fluid Cooled Semiconductor Die Package
Integrated Circuit Chip with Discontinuous Guard Ring
Wire Bonding Machine and Method for Testing Wire Bond Connections
Application:
13/865,185 →
Publication:
US US20140103096A1
Startup Circuits with Native Transistors
Mixed Signal Ip Core Prototyping System
Mems Device with Stress Isolation and Method of Fabrication
Estimation of Sidewall Skew Angles of a Structure
Method of Fabricating Mems Device Having Release Etch Stop Layer
Amplifier Using Nonlinear Drivers
Methods and Systems for Gate Dimension Control in Multi-Gate Structures for Semiconductor Devices
Patent:
8,778,742 →
Application:
13/871,411 →
Selective Gate Oxide Properties Adjustment Using Fluorine
Standard Cell for Semiconductor Device
Patent:
8,759,885 →
Application:
13/873,217 →
Amplifiers and Related Receiver Systems
Method and Apparatus for Accelerating Sparse Matrix Operations in Full Accuracy Circuit Simulation
Integrated Circuit Design Verification Through Forced Clock Glitches
Self-Defining, Low Capacitance Wire Bond Pad
Scalable Split Gate Memory Cell Array
Synchronous Multiple Port Memory with Asynchronous Ports
Patent:
8,848,480 →
Application:
13/873,988 →
Four Port Memory with Multiple Cores
Non-Volatile Memory (Nvm) with Variable Verify Operations
Biasing Split Gate Memory Cell During Power-Off Mode
Method and Apparatus for Generating Gate-Level Activity Data for Use in Clock Gating Efficiency Analysis
Electrostatic Discharge (ESD) Clamp Circuit with High Effective Holding Voltage
Decoder for Determining a Substance or Material Structure of a Detected Object Based on Signals of a Capacitive Sensor and Method for Determining a Substance or Material Structure of a Detected Object Based on Signals of a Capacitive Sensor
Method for Setting Breakpoints, and an Integrated Circuit and Debug Tool Therefor
Method for Bit Rate Control Within a Scalable Video Coding System and System Therefor
Application:
13/880,182 →
Publication:
US US20130251031A1
Integrated Circuit Device and Method for Detecting an Excessive Voltage State
Method of Debugging Software and Corresponding Computer Program Product
Tactile Input Device, Microprocessor System and Method for Controlling a Tactile Input Device
Application:
13/881,157 →
Publication:
US US20130229273A1
Apparatus and Method for Monitoring Operation of an Insulated Gate Bipolar Transistor
Testing an Electrical Connection of a Device Cap
Metal-Oxide-Semiconductor (Mos) Voltage Divider with Dynamic Impedance Control
Semiconductor Device with Notched Gate
System for Measuring Power Consumption of Integrated Circuit
Application:
13/891,214 →
Publication:
US US20140333287A1
Integrated Circuit Power Management Module
Semiconductor Device with Bond and Probe Pads
Application:
13/892,297 →
Publication:
US US20140332811A1
Semiconductor Devices with Different Dielectric Thicknesses
Surface Mount Semiconductor Device with Solder Ball Reinforcement Frame
Patent:
8,836,098 →
Application:
13/894,440 →
Power Plane for Multi-Layered Substrate
Application:
13/894,460 →
Publication:
US US20140339687A1
System for Generating Clock Signal
Patent:
8,760,202 →
Application:
13/895,344 →
System and Method for Creating Logical Radio Link Control (Rlc) and Medium Access Control (Mac) Protocol Data Units (Pdus) in Mobile Communication System
Semiconductor Structure with Sacrificial Anode and Passivation Layer and Method for Forming
Protection Device and Related Fabrication Methods
Protection Device and Related Fabrication Methods
Systems and Methods for Direct Memory Access Coherency Among Multiple Processing Cores
Active Lateral Force Stiction Self-Recovery for Microelectromechanical Systems Devices
Flexible Substrate with Crimping Interconnection
Patent:
8,698,288 →
Application:
13/901,563 →
Method and Apparatus for Self-Test of Successive Approximation Register (Sar) a/D Converter
Integrated Circuit Wake-Up Control System
System and Method for Determining Power Leakage of Electronic Circuit Design
Patent:
8,793,641 →
Application:
13/902,873 →
Data Retention Flip-Flop
Patent:
8,841,952 →
Application:
13/902,974 →
Semiconductor Devices with Multilayer Flex Interconnect Structures
Method of Forming a High Thermal Conducting Semiconductor Device Package
System for Preventing Tampering with Integrated Circuit
I/O Cell Esd System
Self Adjusting Reference for Input Buffer
Patent:
8,872,578 →
Application:
13/906,113 →
Microelectronic Packages Including Patterned Die Attach Material and Methods for the Fabrication Thereof
Stacked Microelectronic Packages Having Sidewall Conductors and Methods for the Fabrication Thereof
Oscillator with Startup Circuitry
Method for Forming an Electrical Connection Between Metal Layers
Multi-Core System Performing Packet Processing with Context Switching
Multiple Data Rate Memory with Read Timing Information
Logic Transistor and Non-Volatile Memory Cell Integration
Fuse/Resistor Utilizing Interconnect and Vias and Method of Making
Methods and Structures for Split Gate Memory
Application:
13/907,845 →
Publication:
US US20140357072A1
Method for Low Power Boot for Microcontroller
Clock Multiplexer
Patent:
8,860,468 →
Application:
13/912,170 →
Optical Wafer and Die Probe Testing
Die Stack with Optical Tsvs
Communication System Die Stack
Integration of a Mems Beam with Optical Waveguide and Deflection in Two Dimensions
Method and Apparatus for Beam Control with Optical Mems Beam Waveguide
Optical Redundancy
Optical Backplane Mirror
Optical Die Test Interface
System and Method for Demodulating an Incoming Signal
Esd Protection Device
Semiconductor Device with Redistributed Contacts
Patent:
8,765,527 →
Application:
13/917,639 →
Mold Cap for Semiconductor Device
Inertial Sensor with Trim Capacitance and Method of Trimming Offset
Application:
13/919,638 →
Publication:
US US20150268268A1
Scaled Sigma Sampling
Patent:
8,806,418 →
Application:
13/921,897 →
Die Fracture Detection and Humidity Protection with Double Guard Ring Arrangement
Lead Frame and Semiconductor Device Using Same
Application:
13/924,623 →
Publication:
US US20140374892A1
Capillary Bonding Tool and Method of Forming Wire Bonds
Application:
13/924,625 →
Publication:
US US20140374467A1
Wire Bonding Method for Flexible Substrates
Application:
13/924,626 →
Publication:
US US20140374151A1
Semiconductor Device with Heat Spreader and Thermal Sheet
Application:
13/924,627 →
Publication:
US US20140374891A1
Semiconductor Sensor Device with Metal Lid
Application:
13/924,628 →
Publication:
US US20140374848A1
Pressure Sensor and Method of Packaging Same
Application:
13/924,633 →
Publication:
US US20140374855A1
Frequency-Domain Amplitude Normalization For Symbol Correlation In Multi-Carrier Systems
Angular Rate Sensor with Quadrature Error Compensation
Frequency-Domain Carrier Blanking For Multi-Carrier Systems
Application:
13/924,940 →
Publication:
US US20140376667A1
Frequency-Domain Frame Synchronization In Multi-Carrier Systems
Frequency-Domain Symbol And Frame Synchronization In Multi-Carrier Systems
System and Method for Low-Latency Addressing in Flash Memory
Patent:
8,886,874 →
Application:
13/925,807 →
Wireless Communication Apparatus and Method
Method for Fabricating Multiple Types of Mems Devices
Reconfigurable Flip-Flop
Non-Volatile Memory (Nvm) and High Voltage Transistor Integration
System with Feature of Saving Dynamic Power of Flip-Flop Banks
Packaged Semiconductor Device
Optimizing Error Parsing in an Integrated Development Environment
Method and System for Recovering from Transistor Aging Using Heating
Multi-Layer Process-Induced Damage Tracking and Remediation
Patent:
8,832,624 →
Application:
13/929,114 →
Semiconductor Package Having Wire Bond Wall to Reduce Coupling
Methods and Structures for a Split Gate Memory Cell Structure
Die-To-Die Inductive Communication Devices and Methods
Die-To-Die Inductive Communication Devices and Methods
Application:
13/930,250 →
Publication:
US US20150004902A1
Integrated Circuits and Methods for Monitoring Forward and Reverse Back Biasing
Method for Detecting Bank Collision at a Memory and Device Therefor
Method, System, and Computer Program Product
Integrated Circuit Device and Method for Calculating a Predicate Value
Application:
13/977,082 →
Publication:
US US20130290686A1
Phased-Array Receiver, Radar System and Vehicle
Integrated Circuit Device, Signal Processing System and Method for Prefetching Lines of Data Therefor
Method for Enabling Calibration During Start-Up of a Micro Controller Unit and Integrated Circuit Therefor
Integrated Circuit and a Method of Power Management of an Integrated Circuit
Error Correcting Device, Method for Monitoring an Error Correcting Device and Data Processing System
Method and Apparatus for Managing Power in a Multi-Core Processor
Switching Arrangement, Integrated Circuit Comprising Same, Method of Controlling a Switching Arrangement, and Related Computer Program Product
Integrated Circuit Device and Method for Performing Conditional Negation of Data
Application:
13/995,190 →
Publication:
US US20130275725A1
Tin-Based Wirebond Structures
Application:
61/835,718 →
Voltage Initialization of a Memory
PCT:
PCT/US2013/038435 ↗
Related Assignments
(24)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 12, 2013
From: MAZIASZ, ROBERT L.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030203/0285 →
Assignment of Assignor's Interest
Apr 30, 2013
From: JAIN, ANKIT; TRIPATHI, VIKAS
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030311/0829 →
Supplement to Ip Security Agreement
Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0627 →
Supplement to Ip Security Agreement
Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 031248/0750 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0804 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0844 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0819 →
Release of Security Interest
Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
Release of Security Interest
Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
Change of Name
Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
Merger
Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
Merger
Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
Corrective Assignment to Correct the Nature of Conveyance Previously Recorded at Reel: 040652 Frame: 0241. Assignor(S) Hereby Confirms the Merger and Change of Name.
Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
Corrective Assignment to Correct the Nature of Conveyance Previously Recorded at Reel: 040632 Frame: 0001. Assignor(S) Hereby Confirms the Merger and Change of Name.
Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
Corrective Assignment to Correct the to Correct the Application No. from 13,883,290 to 13,833,290 Previously Recorded on Reel 041703 Frame 0536. Assignor(S) Hereby Confirms the the Assignment and Assumption of Security Interest in Patents..
Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
Release of Security Interest
Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
Release of Security Interest
Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 042985 Frame 0001. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 042762 Frame 0145. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 038017 Frame 0058. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 039361 Frame 0212. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
Corrective Assignment to Correct the Remove Application 11759915 and Replace It with Application 11759935 Previously Recorded on Reel 037486 Frame 0517. Assignor(S) Hereby Confirms the Assignment and Assumption of Security Interest in Patents.
Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
Corrective Assignment to Correct the Remove Application 11759915 and Replace It with Application 11759935 Previously Recorded on Reel 040928 Frame 0001. Assignor(S) Hereby Confirms the Release of Security Interest.
Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
Corrective Assignment to Correct the Remove Application 11759915 and Replace It with Application 11759935 Previously Recorded on Reel 040925 Frame 0001. Assignor(S) Hereby Confirms the Release of Security Interest.
Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →