IP Library Granted Patent US 9,710,360
Granted Patent B2
US 9,710,360 · App. 13/929,002 · Granted Jul 18, 2017

Optimizing error parsing in an integrated development environment

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,710,360
App. No.
13/929,002
Granted
Jul 18, 2017
Kind
B2
Abstract

A system to enable an integrated development environment to efficiently parse error expressions generated by tools used to generate processing environment-specific executable code, where the tools are external to the integrated development environment, is provided. The system groups error parsers configured to parse the error expressions into two groups: error parsers that handle output from a tool using a single output line of regular expression, and error parsers that require something more than a single output line of regular expression to determine the nature of an error. Embodiments of the system can determine whether a particular output regular expression should be analyzed by a selected set of the error parsers by comparing the output regular expression against a concatenated list of all the regular expressions corresponding to those error parsers that handle output from the tool using a single output line of regular expression.

Claims (37)

1. A method for generating code executable in a target processing environment, the method comprising:

processing a first command line by a first processor, wherein the first command line is generated by an integrated development environment (IDE), said processing the first command line executes a command line tool as a step to produce code executable by the target processing environment and generates one or more output entries;

comparing the one or more output entries to a concatenated regular expression to determine whether the one or more output entries correspond to a first class of error identifiers, wherein the concatenated regular expression comprises a complete set of trigger expressions corresponding to the first class of error identifiers;

if the one or more output entries correspond to the first class of error identifiers, then

determining an error identifier of the first class of error identifiers corresponding to the one or more output entries, and

providing information corresponding to the error identifier and the one or more output entries to the IDE; and

if the one or more output entries do not correspond to the first class of error identifiers and if the one or more output entries correspond to one of a second class of error identifiers, then providing information corresponding to the one of the second class of error identifiers and the one or more output entries to the IDE.

2. The method of claim 1 further comprising:

if the one or more output entries do not correspond to the first class of error identifiers and if the one or more output entries do not correspond to one of the second class of error identifiers, then providing information corresponding to the one or more output entries to the IDE.

3. The method of claim 1 further comprising:

generating the first class of error identifiers using a set of stateless error parsers, wherein a stateless error parser comprises an error parser that uses a single output line of regular expression to determine the nature of an error.

4. The method of claim 3 wherein said determining an error identifier of the first class of error identifiers corresponding to the one or more output entries comprises:

submitting each of the one or more output entries to an error parser of the set of stateless error parsers; and

if the error parser matches a regular expression of the one or more output entries, then the error identifier corresponds to the error parser.

5. The method of claim 1 wherein the second class of error identifiers corresponds to a set of stateful error parsers, wherein a stateful error parser comprises an error parser using multiple output lines of regular expressions to determine the nature of an error.

6. The method of claim 5 wherein said determining if the one or more output entries correspond to one of the second class of error identifiers comprises:

submitting each of the one or more output entries to a stateful error parser of the set of stateful error parsers; and

if the stateful error parser matches regular expressions in the one or more output entries, then the one or more output entries correspond to an error identifier associated with the stateful error parser.

7. A development environment system comprising:

a first system, comprising a first processor and a first memory, configured to provide an integrated development environment, wherein

the first memory stores instructions executable by the first processor to provide the integrated development environment which is configured to generate one or more command lines configured to generate executable code for a target processing environment; and

a second system, comprising a second processor and a second memory and communicatively coupled to the first system, wherein the second memory stores instructions executable by the second processor to provide a set of command line tools configured to process a first command line of the one or more command lines received from the first system, wherein said processing provides a step to generate the executable code for the target processing environment and generates one or more output entries,

compare the one or more output entries to a concatenated regular expression to determine whether the one or more output entries correspond to a first class of error identifiers wherein the concatenated regular expression comprises a complete set of trigger expressions corresponding to the first class of error identifiers,

if the one or more output entries correspond to the first class of error identifiers, then determine an error identifier of the first class of error identifiers corresponding to the one or more output entries and transmit information corresponding to the error identifier and the one or more output entries to the first system, and

if the one or more output entries do not correspond to the first class of error identifiers and if the one or more output entries correspond to one of a second class of error identifiers, then transmit information corresponding to the one of the second class of error identifiers and the one or more output entries to the first system.

8. The system of claim 7 wherein the second memory comprises further instructions executable by the second processor to transmit information corresponding to the one or more output entries to the first system if the one or more output entries do not correspond to the first class of error identifiers and if the one or more output entries do not correspond to one of the second class of error identifiers.

9. The system of claim 7 wherein the second memory comprises further instructions executable by the second processor to generate the first class of error identifiers using a set of stateless error parsers.

10. The system of claim 9 wherein the second memory comprises further instructions executable by the second processor to determine whether the one or more output entries corresponds to the first class of identifiers by being further configured to:

generate a concatenated regular expression comprising each of the first class of error identifiers; and

compare each of the one or more output entries to the concatenated regular expression.

11. The system of claim 9 wherein the second memory comprises further instructions executable by the second processor to determine an error identifier of the first class of error identifiers corresponding to the one or more output entries by being further configured to:

submit each of the one or more output entries to an error parser of the set of stateless error parsers; and

if the error parser matches a regular expression of the one or more output entries, then the error identifier corresponds to the error parser.

12. The system of claim 7 wherein the second class of error identifiers corresponds to a set of stateful error parsers.

13. The system of claim 12 wherein the second memory comprises further instructions executable by the second processor to determine if the one or more output entries correspond to one of the second class of error identifiers by being further configured to:

submit each of the one or more output entries to a stateful error parser of the set of stateful error parsers; and

if the stateful error parser matches regular expressions in the one or more output entries, then the one or more output entries correspond to an error identifier associated with the stateful error parser.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 6, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037445/0592 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0844 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0819 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0804 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 031248/0750 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0627 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0510 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0698 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2013
From: BEAUCHAMP, SERGE
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030710/0028 →