Packaged semiconductor device
View Patent ↗A packaged semiconductor device includes a lead frame having a plurality of leads; a semiconductor die mounted onto the lead frame; and an encapsulant surrounding the semiconductor die. At least a portion of each of the leads is surrounded by the encapsulant, wherein, each lead includes a thin portion external to the encapsulant and a thick portion that is surrounded by the encapsulant, wherein the thin portion is thinner than the thick portion.
1. A packaged semiconductor device, comprising:
a lead frame having a plurality of leads;
a semiconductor die mounted onto the lead frame;
an encapsulant surrounding the semiconductor die, wherein at least a portion of each of the leads is surrounded by the encapsulant, wherein, each lead comprises a knee region of the lead extending external to the encapsulant that is a thin portion and a first thick portion that is surrounded partially by and extends external to the encapsulant and a second thick portion that is a foot portion of the lead, wherein the thin portion is thinner than the first and second thick portions and the thin portion is between the first and second thick portions; and
a bend in a heel/ankle region of the second thick portion adjacent to the foot portion.
2. The packaged semiconductor device of claim 1 , wherein for each lead, the thin portion extends an entire length of the knee region.
3. The packaged semiconductor device of claim 1 , wherein for each lead, a thickness of the thin portion is approximately 50% of a thickness of the first and second thick portions.
4. The packaged semiconductor device of claim 1 , wherein, for each lead, a thickness of the thin portion is in a range of 50-90% of a thickness of the first and second thick portions.
5. A method for forming a packaged semiconductor device, comprising:
attaching a semiconductor die to a lead frame having a plurality of leads to form a lead frame assembly;
encapsulating the lead frame assembly with an encapsulant, wherein the encapsulant surrounds the semiconductor die and at least a portion of each lead of the plurality of leads, wherein each of the plurality of leads comprises a thin portion external to the encapsulant, a first thick portion at one end of the lead that is surrounded partially by and extends from the encapsulant, and a second thick portion at an opposite end of the lead that forms a foot portion, wherein the thin portion is thinner than the first and second thick portions and is between the first and second thick portions; and
forming a bend in a heel/ankle region of the second thick portion, wherein the bend is greater than zero and less than 90 degrees with respect to vertical.
6. The method of claim 5 , further comprising:
after the step of encapsulating, forming the leads.
7. The method of claim 5 , further comprising:
singulating the encapsulated semiconductor die.
8. The method of claim 5 , further comprising:
etching the plurality of leads to form the thin portion of each lead.
9. The method of claim 5 , further comprising:
stamping the lead frame to form the thin portion of each lead.
10. The method of claim 5 , wherein, for each lead, a knee region extends external to the encapsulant, wherein the knee region comprises the thin portion of the lead.
11. The method of claim 10 , wherein, for each lead, the thin portion extends an entire length of the knee region.
12. The method of claim 5 , wherein, for each lead, a thickness of the thin portion is approximately 50% of a thickness of the first and second thick portions.
13. The method of claim 5 , wherein, for each lead, a thickness of the thin portion is in a range of 50 to 90% of a thickness of the first and second thick portions.
14. The method of claim 5 , further comprising:
plating the lead frame prior to attaching the semiconductor die.
15. The method of claim 5 , wherein attaching the semiconductor die comprises:
forming wire bond connections between the semiconductor die and the lead frame.
16. The method of claim 5 , wherein attaching the semiconductor die comprises
forming solder bump connections between the semiconductor die and the lead frame.