IP Library Granted Patent US 9,287,200
Granted Patent B2
US 9,287,200 · App. 13/928,876 · Granted Mar 15, 2016

Packaged semiconductor device

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Quick Facts
Patent No.
US 9,287,200
App. No.
13/928,876
Granted
Mar 15, 2016
Kind
B2
Abstract

A packaged semiconductor device includes a lead frame having a plurality of leads; a semiconductor die mounted onto the lead frame; and an encapsulant surrounding the semiconductor die. At least a portion of each of the leads is surrounded by the encapsulant, wherein, each lead includes a thin portion external to the encapsulant and a thick portion that is surrounded by the encapsulant, wherein the thin portion is thinner than the thick portion.

Claims (30)

1. A packaged semiconductor device, comprising:

a lead frame having a plurality of leads;

a semiconductor die mounted onto the lead frame;

an encapsulant surrounding the semiconductor die, wherein at least a portion of each of the leads is surrounded by the encapsulant, wherein, each lead comprises a knee region of the lead extending external to the encapsulant that is a thin portion and a first thick portion that is surrounded partially by and extends external to the encapsulant and a second thick portion that is a foot portion of the lead, wherein the thin portion is thinner than the first and second thick portions and the thin portion is between the first and second thick portions; and

a bend in a heel/ankle region of the second thick portion adjacent to the foot portion.

2. The packaged semiconductor device of claim 1 , wherein for each lead, the thin portion extends an entire length of the knee region.

3. The packaged semiconductor device of claim 1 , wherein for each lead, a thickness of the thin portion is approximately 50% of a thickness of the first and second thick portions.

4. The packaged semiconductor device of claim 1 , wherein, for each lead, a thickness of the thin portion is in a range of 50-90% of a thickness of the first and second thick portions.

5. A method for forming a packaged semiconductor device, comprising:

attaching a semiconductor die to a lead frame having a plurality of leads to form a lead frame assembly;

encapsulating the lead frame assembly with an encapsulant, wherein the encapsulant surrounds the semiconductor die and at least a portion of each lead of the plurality of leads, wherein each of the plurality of leads comprises a thin portion external to the encapsulant, a first thick portion at one end of the lead that is surrounded partially by and extends from the encapsulant, and a second thick portion at an opposite end of the lead that forms a foot portion, wherein the thin portion is thinner than the first and second thick portions and is between the first and second thick portions; and

forming a bend in a heel/ankle region of the second thick portion, wherein the bend is greater than zero and less than 90 degrees with respect to vertical.

6. The method of claim 5 , further comprising:

after the step of encapsulating, forming the leads.

7. The method of claim 5 , further comprising:

singulating the encapsulated semiconductor die.

8. The method of claim 5 , further comprising:

etching the plurality of leads to form the thin portion of each lead.

9. The method of claim 5 , further comprising:

stamping the lead frame to form the thin portion of each lead.

10. The method of claim 5 , wherein, for each lead, a knee region extends external to the encapsulant, wherein the knee region comprises the thin portion of the lead.

11. The method of claim 10 , wherein, for each lead, the thin portion extends an entire length of the knee region.

12. The method of claim 5 , wherein, for each lead, a thickness of the thin portion is approximately 50% of a thickness of the first and second thick portions.

13. The method of claim 5 , wherein, for each lead, a thickness of the thin portion is in a range of 50 to 90% of a thickness of the first and second thick portions.

14. The method of claim 5 , further comprising:

plating the lead frame prior to attaching the semiconductor die.

15. The method of claim 5 , wherein attaching the semiconductor die comprises:

forming wire bond connections between the semiconductor die and the lead frame.

16. The method of claim 5 , wherein attaching the semiconductor die comprises

forming solder bump connections between the semiconductor die and the lead frame.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 6, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037445/0592 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0804 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0844 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0819 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 031248/0750 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0627 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0510 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0698 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2013
From: HIGGINS, LEO M., III
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030699/0960 →