Self-defining, low capacitance wire bond pad
View Patent ↗A bond pad region is provided that reduces parasitic capacitance generated between bond pad metallization and underlying silicon by reducing the effective area of the bond pad, while maintaining flexibility of wire bond sites and ensuring mechanical integrity of the wire bonds. Embodiments provide, in a region that would be populated by a traditional bus bar bond pad, a small bus bar bond pad that is less than half the area of the region and populating at least a portion of the remaining area with metal tiles that are not electrically connected to the small bus bar bond pad or to each other. The metal tiles provide an attachment area for at least a portion of one or more wire bonds. Only those tiles involved in connection to a wire bond contribute to parasitic capacitance, along with the small bus bar pad.
1. A semiconductor device comprising:
an active device region;
a bond pad region, wherein the bond pad region comprises
a first bond pad electrically coupled to the active device region,
a plurality of bond pad tiles electrically isolated from the first bond pad, each other of the bond pad tiles, and the active device region; and
a wire bond formed on the first bond pad and a subset of the plurality of bond pad tiles.
2. The semiconductor device of claim 1 , wherein
the active device region comprises a MOSFET, and
the first bond pad comprises a bus bar.
3. The semiconductor device of claim 2 wherein the bus bar comprises one-half or less of the bond pad region.
4. The semiconductor device of claim 3 wherein the bond pad region not comprising the bus bar comprises the plurality of bond pad tiles.
5. The semiconductor device of claim 4 further comprising:
a first row of bond pad tiles arranged along an edge of the first bond pad, wherein
a first gap separates the first row of bond pad tiles from the edge of the first bond pad.
6. The semiconductor device of claim 5 , wherein
the first row of bond pad tiles comprises a bond pad tile of the subset of bond pad tiles, and
the gap is less than a distance necessary to mechanically weaken the wire bond to the first bond pad and a bond pad tile of the subset of bond pad tiles.
7. The semiconductor device of claim 6 further comprising:
a second row of bond pad tiles comprising one or more of the subset of the plurality of bond pad tiles.
8. The semiconductor device of claim 1 , wherein
the first bond pad comprises a larger metalized surface area than any of the plurality of bond pad tiles.
9. An apparatus comprising:
a MOSFET device region;
a bond pad region, wherein the bond pad region comprises
a first bond pad electrically coupled to the MOSFET device region,
a plurality of bond pad tiles electrically isolated from the first bond pad, each other of the bond pad tiles, and the active device region; and
a wire bond formed on the first bond pad and one or more of the plurality of bond pad tiles.
10. The apparatus of claim 9 , wherein the first bond pad comprises a bus bar.
11. The apparatus of claim 10 wherein the bond pad region not comprising the bus bar comprises the plurality of bond pad tiles.
12. The apparatus of claim 11 further comprising:
a first row of bond pad tiles arranged along an edge of the first bond pad, wherein
a first gap separates the first row of bond pad tiles from the edge of the first bond pad.
13. The apparatus of claim 12 , wherein
the first row of bond pad tiles comprises a bond pad tile of the one or more bond pad tiles, and
the gap is less than a distance necessary to mechanically weaken the wire bond to the first bond pad and a bond pad tile of the subset of bond pad tiles.
14. The semiconductor device of claim 13 further comprising:
a second row of bond pad tiles comprising a second bond pad tile of the one or more bond pad tiles.
15. The semiconductor device of claim 9 , wherein
the first bond pad comprises a larger metalized surface area than any of the plurality of bond pad tiles.