Granted Patent B2

US 9,590,058 · App. 13/929,924 · Granted Mar 7, 2017

Abstract

Claims (26)

1. A method for forming a split gate memory cell structure using a semiconductor substrate, the method comprising:

forming a gate stack over the semiconductor substrate, wherein the gate stack has a conductive portion with a top surface and a dielectric portion having a bottom surface on the top surface of the conductive portion, the gate stack having a first sidewall along a side of the conductive portion and a side of the dielectric portion;

forming a charge storage layer over the substrate including over the gate stack and along the first sidewall;

forming a conductive layer over the charge storage layer;

etching the conductive layer to leave a first conductive spacer along the first sidewall, wherein a top of the first conductive spacer is above the top surface of the conductive portion and below the top of the dielectric portion;

forming a first sidewall spacer from a lower surface of the first conductive spacer to a first height below the top of the first conductive spacer and a second sidewall spacer along the first sidewall between the top of the first conductive spacer and the top surface of the dielectric portion wherein a portion of the second sidewall spacer is directly above the conductive spacer; and

siliciding the first conductive spacer between the first sidewall spacer and the second sidewall spacer.

2. The method of claim 1 further comprising forming a first source/drain extension in the semiconductor substrate using the first conductive spacer as an implant mask prior to forming the first and second sidewall spacers.

3. The method of claim 1 , further comprising forming a second source/drain extension in the substrate after removing the second conductive spacer.

4. The method of claim 3 , further comprising forming a third sidewall spacer adjacent to the second sidewall.

5. The method of claim 4 further comprising forming a first deep source/drain region in the substrate using the first sidewall spacer as an implant mask and a second deep source/drain region in the substrate using the third sidewall spacer as a mask.

6. The method of claim 5 , further comprising siliciding the substrate over the first and second deep source/drain regions.

7. The method of claim 1 , wherein the forming the conductive layer is further characterized by the conductive layer comprising polysilicon.

8. The method of claim 1 wherein the forming the gate stack is further characterized by the dielectric portion of the gate stack comprising nitride.

9. The method of claim 1 wherein the forming the first and second sidewall spacers is further characterized by the first and second sidewall spacers comprising nitride.

10. The method of claim 1 , wherein the forming the charge storage layer is further characterized by the charge storage layer comprising nanocrystals.

11. A method for forming a split gate memory cell structure using a substrate, comprising:

forming a gate stack comprising a select gate and a dielectric portion overlying the select gate;

forming a charge storage layer over the substrate including over the gate stack;

forming a first sidewall spacer of conductive material along a first sidewall of the gate stack extending past a top of the select gate;

forming a second sidewall spacer of dielectric material along the first sidewall on the first sidewall spacer, wherein a portion of the second sidewall spacer is directly over the first sidewall spacer; and

siliciding a portion of the first sidewall spacer using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.

12. The method of claim 11 , wherein:

the forming the charge storage layer comprises forming a nanocrystal layer;

the forming the first sidewall spacer is further characterized by the first sidewall spacer comprising polysilicon; and

the forming the second sidewall spacer is further characterized by the second sidewall spacer comprising nitride.

Assignments (18)