IP Library Granted Patent US 9,034,679
Granted Patent B2
US 9,034,679 · App. 13/926,652 · Granted May 19, 2015

Method for fabricating multiple types of MEMS devices

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Quick Facts
Patent No.
US 9,034,679
App. No.
13/926,652
Granted
May 19, 2015
Kind
B2
Abstract

A method entails providing a substrate with a structural layer having a thickness. A partial etch process is performed at locations on the structural layer so that a portion of the structural layer remains at the locations. An oxidation process is performed at the locations which consumes the remaining portion of the structural layer and forms an oxide having a thickness that is similar to the thickness of the structural layer. The oxide electrically isolates microstructures in the structural layer, thus producing a structure. A device substrate is coupled to the structure such that a cavity is formed between them. An active region is formed in the device substrate. A short etch process can be performed to expose the microstructures from an overlying oxide layer.

Claims (37)

1. A method comprising:

providing a substrate having a structural layer formed thereon, said structural layer having a first thickness;

removing a first portion of said structural layer at a predetermined location on said structural layer, said first portion of said structural layer having a second thickness that is less than said first thickness so that a second portion of said structural layer remains at said predetermined location; and

performing an oxidation process at said predetermined location to form an oxide, said oxidation process consuming said second portion of said structural layer.

2. A method as claimed in claim 1 wherein said structural layer is formed from polysilicon, and said oxidation process is a local oxidation of silicon process implemented to thermally grow said oxide using said polysilicon of said structural layer.

3. A method as claimed in claim 1 wherein said removing produces conductive microstructures in said structural layer, and said second portion is entirely consumed to provide electrical isolation between adjacent ones of said conductive microstructures.

4. A method as claimed in claim 1 wherein said removing produces microstructures in said structural layer, said microstructures remaining following said performing operation.

5. A method as claimed in claim 1 wherein:

said second thickness of said first portion is approximately one half of said first thickness of said structural layer; and

a third thickness of said oxide following said performing is greater than said first thickness of said structural layer.

6. A method as claimed in claim 1 wherein said structural layer is formed over an oxide layer.

7. A method as claimed in claim 1 further comprising:

following said performing, forming an oxide layer over said structural layer and said oxide; and

planarizing said oxide layer.

8. A method as claimed in claim 1 wherein said substrate is a first substrate, and said method further comprises:

coupling a second substrate to said first substrate with said oxide interposed between said first and second substrates; and

forming an active region of a microelectromechanical systems (MEMS) device in said second substrate.

9. A method as claimed in claim 8 wherein said coupling comprises fusion bonding said second substrate to said first substrate.

10. A method as claimed in claim 8 wherein said second substrate is coupled to said first substrate in spaced apart relationship to produce a cavity between said first and second substrates.

11. A method as claimed in claim 8 further comprising performing said forming following said coupling.

12. A method as claimed in claim 8 further comprising forming an anchor structure extending through said second substrate and through said oxide formed on said first substrate.

13. A method as claimed in claim 8 wherein:

said removing produces a conductive microstructure of a microelectromechanical systems (MEMS) device in said structural layer;

following said performing, forming an oxide layer over said conductive microstructure and said oxide; and

following said coupling, exposing said conductive microstructure from said oxide layer.

14. A method of fabricating a microelectromechanical systems (MEMS) device comprising:

providing a first substrate having a structural layer formed thereon, said structural layer having a first thickness;

removing first portions of said structural layer at predetermined locations on said structural layer to produce conductive microstructures in said structural layer, each of said first portions of said structural layer having a second thickness that is less than said first thickness so that second portions of said structural layer remain at said predetermined locations;

performing an oxidation process at said predetermined locations to form an oxide, said oxidation process entirely consuming said second portions of said structural layer to provide electrical isolation between adjacent ones of said conductive microstructures;

coupling a second substrate to said first substrate with said oxide interposed between said first and second substrates; and

forming an active region of said microelectromechanical systems (MEMS) device in said second substrate following said coupling.

15. A method as claimed in claim 14 wherein said structural layer is formed from polysilicon, and said oxidation process is a local oxidation of silicon process implemented to thermally grow said oxide using said polysilicon of said structural layer.

16. A method as claimed in claim 14 further comprising:

following said performing, forming an oxide layer over said structural layer and said oxide;

planarizing said oxide layer; and

following said coupling, exposing said conductive microstructures from said oxide layer.

17. A method as claimed in claim 14 wherein said second substrate is coupled to said first substrate in spaced apart relationship to produce a cavity between said first and second substrates, said cavity underlying said active region of said MEMS device, and said conductive microstructures underlying said cavity.

Assignments (30)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
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Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
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MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 6, 2016
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2013
From: LIU, LIANJUN
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