Granted Patent B2

US 9,224,861 · App. 13/890,402 · Granted Dec 29, 2015

Abstract

Claims (58)

1. A semiconductor device comprising:

a semiconductor substrate;

a body region disposed in the semiconductor substrate and having a first conductivity type;

a source region disposed in the semiconductor substrate adjacent the body region and having a second conductivity type;

a drain region disposed in the semiconductor substrate, having the second conductivity type, and laterally spaced from the source region along a major surface of the semiconductor substrate to define a conduction path;

a gate structure supported by the semiconductor substrate, configured to control formation of a channel in the conduction path during operation, and having a side adjacent the source region that comprises a notch, the notch defining a notch area; and

a notch region disposed in the semiconductor substrate in the notch area and having the first conductivity type, wherein a channel length is less in portions of the conduction path beneath the gate structure having the notch region than a channel length is in portions of the conduction path beneath the gate structure not having the notch region.

2. The semiconductor device of claim 1 , wherein:

the body region comprises a well within which the source region and a body contact region are disposed; and

the body contact region comprises the notch region.

3. The semiconductor device of claim 1 , wherein:

the conduction path is oriented along a first lateral direction; and

the side of the gate structure comprising the notch is oriented along a second lateral direction transverse to the first lateral direction.

4. The semiconductor device of claim 3 , wherein:

the source region is one of a plurality of constituent source regions of a composite source region; and

the plurality of constituent source regions are distributed and spaced from one another along the second lateral direction.

5. The semiconductor device of claim 4 , wherein:

the side of the gate structure comprises a plurality of teeth to define a plurality of notches including the notch; and

each constituent source region does not extend in the second lateral direction beyond a respective tooth of the plurality of teeth to which the constituent source region is adjacent.

6. The semiconductor device of claim 1 , wherein the notch is one of a plurality of notches in the side of the gate structure adjacent the source region.

7. The semiconductor device of claim 6 , wherein the plurality of notches are regularly distributed along the side of the gate structure.

8. The semiconductor device of claim 6 , wherein a lateral spacing between adjacent notches of the plurality of notches falls in a range from about 0.5 μm to about 2 μm.

9. The semiconductor device of claim 6 , wherein a lateral width of each notch falls in a range from about 0.2 μm to about 2 μm.

10. The semiconductor device of claim 1 , wherein the side of the gate structure includes, for each notch, an inner sidewall and a pair of lateral sidewalls that extend laterally from the inner sidewall in a rectilinear arrangement.

11. An electronic apparatus comprising:

a semiconductor substrate; and

a field-effect transistor device in the semiconductor substrate, the field-effect transistor device comprising:

a first semiconductor region having a first conductivity type;

a second semiconductor region adjacent the first semiconductor region and having a second conductivity type;

a third semiconductor region having the second conductivity type and laterally spaced from the second semiconductor region along a major surface of the semiconductor substrate to define a conduction path;

a gate structure supported by the semiconductor substrate, configured to control formation of a channel in the conduction path during operation, and having a side adjacent the second semiconductor region that comprises a plurality of notches, each notch defining a respective notch area; and

a plurality of fourth semiconductor regions having the first conductivity type, each fourth semiconductor region being disposed in one of the notch areas, wherein a channel length is less in portions of the gate structure having a notch region disposed in the semiconductor substrate in the notch area than a channel length is in portions of the gate structure not having the notch region.

12. The electronic apparatus of claim 11 , wherein the fourth semiconductor regions are regularly distributed along the side of the gate structure.

13. The electronic apparatus of claim 11 , wherein:

the first semiconductor region comprises a well within which the second semiconductor region and a contact region for the first semiconductor region are disposed; and

the contact region comprises the plurality of fourth semiconductor regions.

14. The electronic apparatus of claim 11 , wherein:

the conduction path is oriented along a first lateral direction; and

the side of the gate structure comprising the plurality of notches is oriented along a second lateral direction transverse to the first lateral direction.

15. The electronic apparatus of claim 14 , wherein:

the second semiconductor region is one of a plurality of constituent source regions of a composite source region; and

the plurality of constituent source regions are distributed and spaced from one another along the second lateral direction.

16. The electronic apparatus of claim 15 , wherein:

the side of the gate structure comprises a plurality of teeth to define the plurality of notches; and

each constituent source region does not extend in the second lateral direction beyond a respective tooth of the plurality of teeth to which the constituent source region is adjacent.

17. A method of fabricating semiconductor device, the method comprising:

forming a body region in a semiconductor substrate, the body region having a first conductivity type;

forming a gate structure supported by the semiconductor substrate; and

forming source and drain regions laterally spaced apart from one another along a major surface of the semiconductor substrate in the semiconductor substrate, the source region being disposed adjacent the body region, the source and drain regions having a second conductivity type;

wherein the gate structure has a side adjacent the source region that comprises a notch, the notch defining a notch area; and

wherein forming the source and drain regions comprises defining a layout of the source region such that a notch region in the semiconductor substrate in the notch area has the first conductivity type, wherein a channel length is less in portions of the conduction path beneath the gate structure having the notch region than a channel length is in portions of the conduction path beneath the gate structure not having the notch region.

18. The method of claim 17 , further comprising forming a body contact region in the semiconductor substrate and having the first conductivity type, a portion of the body contact region being disposed in the notch area to form the notch region.

19. The method of claim 17 , wherein:

the layout of the source region is configured such that the source region is one of a plurality of constituent source regions of a composite source region; and

the plurality of constituent source regions are distributed and spaced from one another along a first lateral direction transverse to a conduction path of the semiconductor device defined by the source and drain regions.

20. The method of claim 19 , wherein:

the side of the gate structure comprises a plurality of teeth to define the notch; and

each constituent source region does not extend in the first lateral direction beyond a respective tooth of the plurality of teeth to which the constituent source region is adjacent.

Assignments (29)