IP Library Granted Patent US 8,878,348
Granted Patent B2
US 8,878,348 · App. 13/854,137 · Granted Nov 4, 2014

Semiconductor device and method of assembling same

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Quick Facts
Patent No.
US 8,878,348
App. No.
13/854,137
Granted
Nov 4, 2014
Kind
B2
Abstract

A semiconductor device has a die support and external leads formed integrally from a single sheet of electrically conductive material. A die mounting substrate is mounted on the die support, with bonding pads coupled to respective external connection pads on an external connector side of the substrate. A die is attached to the die mounting substrate with die connection pads. Bond wires selectively electrically couple the die connection pads to the external leads and the bonding pads and electrically conductive external protrusions are mounted to the external connection pads. An encapsulant covers the die and bond wires. The external protrusions are located at a central region of a surface mounting side of the package and the external leads project outwardly from locations near the die support towards peripheral edges of the package.

Claims (34)

1. A semiconductor device, comprising:

a die support and external leads formed integrally from a single sheet of electrically conductive material;

a die mounting substrate having a die mounting side and an opposite external connector side mounted on the die support, wherein the die mounting side has bonding pads coupled to respective external connection pads on the external connector side of the substrate;

a semiconductor die having a die support mounting surface attached to the die mounting side of the die mounting substrate, and an opposite die connection pad surface with associated die connection pads, wherein the die connection pads are circuit nodes of the semiconductor die;

bond wires selectively electrically coupling the die connection pads to the external leads and the bonding pads;

electrically conductive external protrusions attached to the external connection pads; and

an encapsulating material at least partially encapsulating the die and the bond wires,

wherein the external protrusions are located at a central region of a surface mounting side of the device, and the external leads project outwardly from the surface mounting side from locations proximal to the die support towards peripheral edges of the device.

2. The semiconductor device of claim 1 , wherein the die support includes two spaced parallel members at least partially enclosing the central region.

3. The semiconductor device of claim 2 , wherein the die mounting substrate spans the two spaced parallel members.

4. The semiconductor device of claim 1 , wherein the die support is a frame enclosing the central region.

5. The semiconductor device of claim 4 , wherein the frame is rectangular.

6. The semiconductor device of claim 1 , wherein the external protrusions form a grid array.

7. The semiconductor device of claim 1 , wherein the external protrusions are balls forming a ball grid array.

8. The semiconductor device of claim 1 , wherein each of the external leads has a peripheral end flush with a one of the peripheral edges.

9. The semiconductor device of claim 8 , wherein each of the peripheral edges has a peripheral end with at least one of the external leads flush therewith.

10. The semiconductor device of claim 1 , wherein channels are formed in the surface mounting side of the encapsulating material between the die support and the external leads.

11. The semiconductor device of claim 10 , wherein each of the channels is parallel to a peripheral edge.

12. The semiconductor device of claim 1 , wherein the die mounting substrate has thermally conductive runners thermally coupling the semiconductor die to the die support.

13. A method for assembling a semiconductor device, the method comprising:

providing a die support and external leads formed integrally from a single sheet of electrically conductive material;

mounting a die mounting substrate on the die support, the die mounting substrate having a die mounting side and an opposite external connector side mounted on the die support, wherein the die mounting side has bonding pads coupled to respective external connection pads on the external connector side of the substrate;

mounting a semiconductor die to the die mounting substrate, the semiconductor die having a die support mounting surface attached to the die mounting side of the die mounting substrate, and an opposite die connection pad surface with associated die connection pads, wherein the die connection pads are circuit nodes of the semiconductor die;

selectively electrically coupling the die connection pads to the external leads and the bonding pads;

attaching electrically conductive external protrusions to the external connection pads; and

encapsulating at least part of the die with an encapsulating material to form the semiconductor device,

wherein the external protrusions are located at a central region of a surface mounting side of the device and the external leads project outwardly on the surface mounting side of the device from locations proximal to the die support towards peripheral edges of the device.

14. The method for assembling a semiconductor device of claim 13 , further including electrically isolating the die support from the leads.

15. The method for assembling a semiconductor device of claim 14 , wherein the electrically isolating the die support from the leads includes cutting channels therebetween.

16. The method for assembling a semiconductor device of claim 15 , wherein the channels are cut into the surface mounting side of the encapsulating material.

17. The method for assembling a semiconductor device of claim 13 , wherein the die support includes two spaced parallel members at least partially enclosing the central region.

18. The method for assembling a semiconductor device of claim 17 , wherein the die mounting substrate spans the two spaced parallel members.

19. The method for assembling a semiconductor device of claim 13 , wherein the external protrusions form a grid array.

20. The method for assembling a semiconductor device of claim 13 , wherein each of the external leads has a peripheral end flush with one of the peripheral edges.

Assignments (24)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0844 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0819 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0804 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2014
From: HUANG, MEIQUAN; WANG, HUAN; WANG, JINGSHENG; ZHOU, NAIKUO
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 033834/0766 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 031248/0750 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0627 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0510 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBER TO BE CORRECTED FROM 12/854,137 TO 13/854,137 PREVIOUSLY RECORDED ON REEL 030120 FRAME 0091. ASSIGNOR(S) HEREBY CONFIRMS THE THE APPLICATION NUMBER TO BE CHANGED FROM 12854137 TO 13854137. Recorded Apr 3, 2013
From: HUANG, MEIQUAN; WANG, HUAN; WANG, JINSHENG; ZHOU, NAIKUO
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030148/0887 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2013
From: HUANG, MEIQUAN; WANG, HUAN; WANG, JINSHENG; ZHOU, NAIKUO
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030120/0091 →