Amplifiers and related receiver systems
View Patent ↗Apparatus are provided for amplifier circuits and related receiver systems. An amplifier circuit includes a first common-source amplification stage and a second common-source amplification stage. The input of the second common-source amplification stage is coupled to the output of the first common-source amplification stage such that the first common-source amplification stage generates a first amplified signal, and the second common-source amplification stage generates a second amplified signal based on the first amplified signal. The first common-source amplification stage is coupled to a first node and the second common-source amplification stage is coupled to a second node, wherein the common-source amplification stages are configured such that a current between the first node and the second node flows in series through the common-source amplification stages.
1. An amplifier circuit comprising:
a first transistor having a source terminal connected to a first reference voltage node, a gate terminal connected to a first input node, and a drain terminal;
a second transistor having a source terminal connected to the drain terminal of the first transistor, a gate terminal connected to a second reference voltage node, and a drain terminal;
a third transistor having a source terminal connected to the second reference voltage node, a gate terminal connected to the drain terminal of the second transistor, and a drain terminal; and
a fourth transistor having a source terminal connected to the drain terminal of the third transistor, a gate terminal connected to the first reference voltage node, and a drain terminal connected to a first output node.
2. The amplifier circuit of claim 1 , wherein:
the first transistor comprises a first N-type transistor;
the second transistor comprises a second N-type transistor;
the third transistor comprises a first P-type transistor; and
the fourth transistor comprises a second P-type transistor.
3. The amplifier circuit of claim 1 , further comprising:
a first tank circuit coupled between the drain terminal of the second transistor and a third reference voltage node; and
a second tank circuit coupled between the drain terminal of the fourth transistor and the third reference voltage node.
4. The amplifier circuit of claim 3 , wherein:
the first tank circuit is configured to provide a first resonant frequency;
the second tank circuit is configured to provide a second resonant frequency; and
the first resonant frequency and the second resonant frequency are different.
5. The amplifier circuit of claim 3 , wherein:
the first tank circuit is configured to provide a first resonant frequency that is less than a carrier frequency; and
the second tank circuit being configured to provide a second resonant frequency that is greater than the carrier frequency.
6. The amplifier circuit of claim 3 , wherein:
the first tank circuit comprises a first inductive element connected between the drain terminal of the second transistor and the third reference voltage node; and
the second tank circuit comprises a second inductive element connected between the drain terminal of the fourth transistor and the third reference voltage node.
7. The amplifier circuit of claim 3 , wherein current between the first reference voltage node and the second reference voltage node flows in series through the first tank circuit and the second tank circuit.
8. The amplifier circuit of claim 3 , further comprising a capacitive element coupled between the third reference voltage node and the first reference voltage node.
9. The amplifier circuit of claim 8 , wherein the capacitive element is configured to provide a virtual ground reference voltage for an alternating current electrical signal at the first output node.
10. The amplifier circuit of claim 3 , further comprising a first capacitive element coupled between the third reference voltage node and the first reference voltage node.
11. The amplifier circuit of claim 10 , further comprising
a fifth transistor having a source terminal connected to the first reference voltage node, a gate terminal connected to a second input node, and a drain terminal;
a sixth transistor having a source terminal connected to the drain terminal of the fifth transistor, a gate terminal connected to the second reference voltage node, and a drain terminal, the first tank circuit being coupled between the drain terminal of the sixth transistor and the third reference voltage node;
a seventh transistor having a source terminal connected to the second reference voltage node, a gate terminal connected to the drain terminal of the sixth transistor, and a drain terminal; and
an eighth transistor having a source terminal connected to the drain terminal of the seventh transistor, a gate terminal connected to the first reference voltage node, and a drain terminal connected to a second output node, the second tank circuit being coupled between the drain terminal of the eighth transistor and the third reference voltage node.
12. The amplifier circuit of claim 11 , wherein:
the first tank circuit comprises:
a first inductive element connected between the drain terminal of the second transistor and the third reference voltage node;
a second inductive element connected between the drain terminal of the sixth transistor and the third reference voltage node; and
a second capacitive element connected between the drain terminal of the second transistor and the drain terminal of the sixth transistor; and
the second tank circuit comprises:
a third inductive element connected between the drain terminal of the fourth transistor and the third reference voltage node;
a fourth inductive element connected between the drain terminal of the eighth transistor and the third reference voltage node; and
a third capacitive element connected between the drain terminal of the fourth transistor and the drain terminal of the eighth transistor.
13. The amplifier circuit of claim 12 , wherein:
the first transistor comprises a first N-type transistor;
the second transistor comprises a second N-type transistor;
the fifth transistor comprises a third N-type transistor;
the sixth transistor comprises a fourth N-type transistor;
the third transistor comprises a first P-type transistor;
the fourth transistor comprises a second P-type transistor;
the seventh transistor comprises a third P-type transistor; and
the eighth transistor comprises a fourth P-type transistor.
14. The amplifier circuit of claim 1 , wherein:
the first transistor and the second transistor are configured as a first transistor stack coupled between a first amplification stage output and the first reference voltage node;
the third transistor and the fourth transistor are configured as a second transistor stack coupled between the second reference voltage node and the first output node; and
current between the first reference voltage node and the second reference voltage node flows in series through the first transistor stack and the second transistor stack.
15. A receiver system comprising:
an antenna configured to generate an electrical signal in response to an electromagnetic signal; and
the amplifier circuit of claim 1 , wherein the amplifier circuit is configured to generate an output signal representative of the electrical signal at the first output node based on an input signal representative of the electrical signal at the first input node.
16. The receiver system of claim 15 , wherein the amplifier circuit comprises:
a first tank circuit coupled between the drain terminal of the second transistor and a third reference voltage node, the first tank circuit being configured to provide a first resonant frequency that is less than a carrier frequency of the electromagnetic signal; and
a second tank circuit coupled between the drain terminal of the fourth transistor and the third reference voltage node, the second tank circuit being configured to provide a second resonant frequency that is greater than the carrier frequency of the electromagnetic signal.
17. The receiver system of claim 16 , wherein the carrier frequency is 2.45 GHz.
18. An amplifier circuit comprising:
a first common-source amplification stage including a first transistor stack coupled between a first amplification stage output and a first reference voltage node, the first transistor stack comprising:
a first transistor having a source terminal connected to the first reference voltage node, a gate terminal connected to a input node, and a drain terminal;
a second transistor having a source terminal connected to the drain terminal of the first transistor, a gate terminal connected to a second reference voltage node, and a drain terminal; and
a second common-source amplification stage including a second transistor stack coupled between the second reference voltage node and an output node, the second transistor stack comprising:
a third transistor having a source terminal connected to the second reference voltage node, a gate terminal connected to the drain terminal of the second transistor, and a drain terminal; and
a fourth transistor having a source terminal connected to the drain terminal of the third transistor, a gate terminal connected to the first reference voltage node, and a drain terminal connected to the output node.
19. The amplifier circuit of claim 18 , wherein a current between the first reference voltage node and the second reference voltage node flows in series through the first common-source amplification stage and the second common-source amplification stage.
20. The amplifier circuit of claim 18 , wherein:
the first common-source amplification stage includes a third transistor stack comprising:
a fifth transistor having a source terminal connected to the first reference voltage node, a gate terminal connected to a second input node, and a drain terminal; and
a sixth transistor having a source terminal connected to the drain terminal of the fifth transistor, a gate terminal connected to the second reference voltage node, and a drain terminal; and
the second common-source amplification stage includes a fourth transistor stack comprising:
a seventh transistor having a source terminal connected to the second reference voltage node, a gate terminal connected to the drain terminal of the sixth transistor, and a drain terminal; and
an eighth transistor having a source terminal connected to the drain terminal of the seventh transistor, a gate terminal connected to the first reference voltage node, and a drain terminal connected to a second output node.