Method and system for recovering from transistor aging using heating
View Patent ↗A mechanism is provided for extending useable lifetimes of semiconductor devices that are subject to trapped charge carriers in a gate dielectric. Embodiments of the present invention provide heat to the gate dielectric region from one or more sources, where the heat sources are included in a package along with the semiconductor device. It has been determined that heat, when applied during a period when the channel region of a transistor is in accumulation mode or is not providing a current across the channel, can at least partially recover the device from trapped charge carrier effects. Embodiments of the present invention supply heat to the affected gate dielectric region using mechanisms available where the semiconductor device is used (e.g., in the field).
1. A semiconductor device package comprising:
a semiconductor device die comprising a semiconductor device subject to a shift in threshold voltage due to trapped charge carriers in a gate dielectric layer of the semiconductor device;
a heating device located within the semiconductor device package and configured to selectively provide heat to the gate dielectric layer of the semiconductor device, wherein
the heat is sufficient to decrease the shift in threshold voltage due to trapped charge carriers in the gate dielectric layer of the semiconductor device;
an n-well of the semiconductor device configured in thermal contact with the gate dielectric layer; and
two or more electrical contacts to the n-well configured to provide an electrical current through the n-well, wherein
a resistance of the n-well provides the heat to the gate dielectric layer in response to the electrical current.
2. The semiconductor device package of claim 1 wherein said selectively providing heat to the gate dielectric layer comprises applying heat when the semiconductor device is in one or more of accumulation mode or having zero current between source and drain of the semiconductor device.
3. The semiconductor device package of claim 1 wherein the semiconductor device die comprises the heating device.
4. The semiconductor device package of claim 1 wherein the semiconductor device die further comprises:
a plurality of semiconductor devices each subject to a rising shift in threshold voltage due to trapped charge carriers in corresponding gate dielectric layers of the plurality of semiconductor devices, wherein
the corresponding gate dielectric layers are formed in thermal contact with the n-well, and
said providing the electrical current to the n-well generates heat sufficient to decrease a magnitude of the shift in threshold voltage due to trapped charge carriers in the corresponding gate dielectric layers of each of the plurality of semiconductor devices.
5. A semiconductor device package comprising:
a semiconductor device die comprising a semiconductor device subject to a shift in threshold voltage due to trapped charge carriers in a gate dielectric layer of the semiconductor device;
a heating device located within the semiconductor device package and configured to selectively provide heat to the gate dielectric layer of the semiconductor device, wherein
the heat is sufficient to decrease the shift in threshold voltage due to trapped charge carriers in the gate dielectric layer of the semiconductor device, and
the semiconductor device die comprises the heating device;
a gate stack of the semiconductor device, wherein the gate stack comprises
the gate dielectric layer and a resistive layer,
a conductive gate layer formed over the gate dielectric layer, and
the resistive layer formed over the conductive gate layer, wherein a heater dielectric layer electrically isolates the resistive layer from the conductive gate layer,
two or more electrical contacts to the resistive layer configured to provide an electrical current through the resistive layer, wherein
a resistance of the resistive layer provides the heat to the gate dielectric layer in response to the electrical current.
6. A semiconductor device package comprising:
a semiconductor device die comprising a semiconductor device subject to a shift in threshold voltage due to trapped charge carriers in a gate dielectric layer of the semiconductor device; and
a heating device located within the semiconductor device package and configured to selectively provide heat to the gate dielectric layer of the semiconductor device, wherein
the heat is sufficient to decrease the shift in threshold voltage due to trapped charge carriers in the gate dielectric layer of the semiconductor device, and
the heating device comprises a heating device die thermally coupled to a major surface of the semiconductor device die.
7. The semiconductor device package of claim 6 , wherein the heating device die comprises a heating resistor configured to provide the heat in response to an electrical current passed through the heating resistor.
8. The semiconductor device package of claim 6 wherein the semiconductor device package further comprises:
one or more thermally conductive conduits having a first end at or near the major surface of the semiconductor device die and a second end at or near the gate dielectric layer, wherein the thermally conductive conduits are configured to transmit the heat generated by the heating device die to the gate dielectric layer.
9. An apparatus comprising:
a semiconductor device package comprising
a semiconductor device die comprising a semiconductor device subject to a shift in threshold voltage due to trapped charge carriers in a gate dielectric layer of the semiconductor device, and
a heating device located within the semiconductor device package and configured to selectively provide heat to the gate dielectric layer of the semiconductor device, wherein
the heating device comprises a heating device die thermally coupled to a major surface of the semiconductor device die, and
the heat is sufficient to decrease a magnitude of the shift in threshold voltage due to trapped charge carriers in the gate dielectric layer of the semiconductor device;
a first power source configured to supply voltage and current sufficient to operate logic of the semiconductor device die; and
a second power source configured to supply voltage and current sufficient to operate the heating device, wherein the voltage and current sufficient to operate the heating device are not equal to the voltage and current sufficient to operate the logic of the semiconductor device.
10. The apparatus of claim 9 wherein said selectively providing heat to the gate dielectric layer comprises applying heat when the semiconductor device is in one or more of accumulation mode or having zero current between source and drain of the semiconductor device.