Reconfigurable flip-flop
View Patent ↗A device ( 300, 1000 ) provides a dual-edge triggered flip-flop (DETFF) that is reconfigurable to a master-slave flip-flop (MSFF). The device includes a reconfigurable MUX-D flip-flop including two distinct circuit configurations. In a first configuration, two latches or storage elements ( 340, 360, 1040, 1060 ) are operating in series to provide a MUX-D flip-flop. In a second configuration, the storage elements ( 340, 360, 1040, 1060 ) are operating in parallel to provide a dual-edge triggered flip-flop (DETFF).
1. A reconfigurable flip-flop circuit, comprising:
an input;
a common output;
a first storage element including an input electrically coupled to the input through at least a first storage element input switch, and an output electrically coupled to a first storage element output switch;
a second storage element including an input electrically coupled to the input through at least a second storage element input switch, and an output electrically coupled to a second storage element output switch;
a third storage element including an input/output node electrically coupled to the second storage element output switch, and the input/output node electrically coupled to the common output; and
control circuitry, the control circuitry configured such that during a first mode of operating, the control circuitry configures each of the first storage element and the second storage element to operate as a latch in a dual-edge triggered flip-flop, and during a second mode of operating, the control circuitry configures the second storage element to operate as a latch in a master-slave flip-flop,
wherein during the first mode of operating, the control circuitry couples in parallel the first storage element and the second storage element, and
wherein the first storage element output switch and the second storage element output switch are coupled to the common output.
2. The reconfigurable flip-flop circuit of claim 1 , wherein the input further comprises
a first inverter disposed between a data input and the input, and
a second inverter disposed between a test input and the input,
wherein the control circuitry selectively controls whether information from the data input or the test input is transmitted to the input.
3. The reconfigurable flip-flop circuit of claim 1 ,
wherein the first storage element further includes:
at least a first inverter including an input electrically coupled to the input and an output, and
at least a second inverter including an input electrically coupled to the output of the first inverter and an output electrically coupled to the input of the first inverter;
wherein the second storage element further includes:
at least a third inverter including an input electrically coupled to the input and an output, and
at least a fourth inverter including an input electrically coupled to the output of the third inverter and an output electrically coupled to the input of the third inverter; and
wherein the third storage element further includes:
at least a fifth inverter including an input electrically coupled to the common output and an output, and
at least a sixth inverter including an input electrically coupled to the output of the fifth inverter and an output electrically coupled to the input of the fifth inverter.
4. The reconfigurable flip-flop circuit of claim 2 , wherein the first storage element further includes:
at least a first inverter including an input electrically coupled to the input and an output, and
at least a second inverter including an input electrically coupled to the output of the first inverter and an output electrically coupled to the input of the first inverter.
5. The reconfigurable flip-flop circuit of claim 4 , wherein the second storage element further includes:
at least a third inverter including an input electrically coupled to the input, and an output, and
at least a fourth inverter including an input electrically coupled to the output of the third inverter and an output electrically coupled to the input of the third inverter.
6. The reconfigurable flip-flop circuit of claim 5 , wherein the third storage element includes
an input/output node electrically coupled to the second storage element output switch, and
the input/output node electrically coupled to the common output, thereby operating as a hold latch during the first mode of operating.
7. A reconfigurable flip-flop circuit, comprising:
an input;
a common output;
a first storage element including an input electrically coupled to the input through at least a first storage element input switch, and an output electrically coupled to a first storage element output switch;
a second storage element including an input electrically coupled to the input through at least a second storage element input switch, and an output electrically coupled to a second storage element output switch;
a third storage element including an input/output node electrically coupled to the second storage element output switch, and the input/output node electrically coupled to the common output;
control circuitry that configures each of the first storage element and the second storage element to operate as a latch in a dual-edge triggered flip-flop during a first mode of operating, and that configures the second storage element to operate as a latch in a master-slave flip-flop during a second mode of operating; and
a cross-storage element switch with a first terminal and a second terminal, the first terminal electrically coupled to the output of the first storage element and the second terminal electrically coupled to the input of the second storage element,
wherein the first storage element output switch and the second storage element output switch are coupled to the common output.
8. The reconfigurable flip-flop circuit of claim 7 , wherein the input further comprises
a first inverter disposed between a data input and the input, and
a second inverter disposed between a test input and the input,
wherein the control circuitry selectively controls whether information from the data input or the test input is transmitted to the input.
9. The reconfigurable flip-flop circuit of claim 7 ,
wherein the first storage element further includes:
at least a first inverter including an input electrically coupled to the input and an output, and
at least a second inverter including an input electrically coupled to the output of the first inverter and an output electrically coupled to the input of the first inverter;
wherein the second storage element further includes:
at least a third inverter including an input electrically coupled to the input and an output, and
at least a fourth inverter including an input electrically coupled to the output of the third inverter and an output electrically coupled to the input of the third inverter; and
wherein the third storage element further includes:
at least a fifth inverter including an input electrically coupled to the common output and an output, and
at least a sixth inverter including an input electrically coupled to the output of the fifth inverter and an output electrically coupled to the input of the fifth inverter.
10. The reconfigurable flip-flop circuit of claim 8 , wherein the first storage element further includes:
at least a first inverter including an input electrically coupled to the input and an output, and
at least a second inverter including an input electrically coupled to the output of the first inverter and an output electrically coupled to the input of the first inverter.
11. The reconfigurable flip-flop circuit of claim 10 , wherein the second storage element further includes:
at least a third inverter including an input electrically coupled to the input, and an output, and
at least a fourth inverter including an input electrically coupled to the output of the third inverter and an output electrically coupled to the input of the third inverter.
12. The reconfigurable flip-flop circuit of claim 11 , wherein the third storage element includes
an input/output node electrically coupled to the second storage element output switch, and
the input/output node electrically coupled to the common output, thereby operating as a hold latch during the first mode of operating.
13. A reconfigurable flip-flop circuit, comprising:
an input;
a common output;
a first storage element including an input electrically coupled to the input through at least a first storage element input switch, and an output electrically coupled to a first storage element output switch;
a second storage element including an input electrically coupled to the input through at least a second storage element input switch, and an output electrically coupled to a second storage element output switch;
a third storage element including an input/output node electrically coupled to the second storage element output switch, and the input/output node electrically coupled to the common output;
control circuitry that configures each of the first storage element and the second storage element to operate as a latch in a dual-edge triggered flip-flop during a first mode of operating, and that configures the second storage element to operate as a latch in a master-slave flip-flop during a second mode of operating; and
a cross-storage element switch with a first terminal and a second terminal, the first terminal electrically coupled to the output of the first storage element and the second terminal electrically coupled to the input of the second storage element,
wherein during the first mode of operating, the control circuitry couples in parallel the first storage element and the second storage element, and during the second mode of operating, the control circuitry couples in series the first storage element and the second storage element through at least the cross-storage element switch.
14. The reconfigurable flip-flop circuit of claim 13 , wherein the input further comprises
a first inverter disposed between a data input and the input, and
a second inverter disposed between a test input and the input,
wherein the control circuitry selectively controls whether information from the data input or the test input is transmitted to the input.
15. The reconfigurable flip-flop circuit of claim 13 , wherein the first storage element further includes:
at least a first inverter including an input electrically coupled to the input and an output, and
at least a second inverter including an input electrically coupled to the output of the first inverter and an output electrically coupled to the input of the first inverter.
16. The reconfigurable flip-flop circuit of claim 15 , wherein the second storage element further includes:
at least a third inverter including an input electrically coupled to the input and an output, and
at least a fourth inverter including an input electrically coupled to the output of the third inverter and an output electrically coupled to the input of the third inverter.
17. The reconfigurable flip-flop circuit of claim 16 , wherein the third storage element further includes:
at least a fifth inverter including an input electrically coupled to the common output and an output, and
at least a sixth inverter including an input electrically coupled to the output of the fifth inverter and an output electrically coupled to the input of the fifth inverter.
18. The reconfigurable flip-flop circuit of claim 13 , wherein the first storage element further includes:
at least a first inverter including an input electrically coupled to the input and an output, and
at least a second inverter including an input electrically coupled to the output of the first inverter and an output electrically coupled to the input of the first inverter.
19. The reconfigurable flip-flop circuit of claim 18 , wherein the second storage element further includes:
at least a third inverter including an input electrically coupled to the input, and an output, and
at least a fourth inverter including an input electrically coupled to the output of the third inverter and an output electrically coupled to the input of the third inverter.
20. The reconfigurable flip-flop circuit of claim 19 , wherein the third storage element includes
an input/output node electrically coupled to the second storage element output switch, and
the input/output node electrically coupled to the common output, thereby operating as a hold latch during the first mode of operating.