Granted Patent B1

US 8,860,468 · App. 13/912,170 · Granted Oct 14, 2014

Abstract

Claims (30)

1. A clock multiplexer for providing an output clock signal, comprising:

a first input stage for outputting a first clock signal, wherein the first input stage includes,

a first flip-flop having an input terminal, a clock input terminal for receiving the first clock signal, and a reset input terminal for receiving a select signal, wherein the first flip-flop outputs a first enable signal at an output terminal thereof;

a first latch having an input terminal connected to the output terminal of the first flip-flop for receiving the first enable signal, and a clock input terminal for receiving the first clock signal, wherein the first latch outputs a first output signal at an output terminal thereof and an inverted first output signal at an inverting output terminal thereof; and

a first logic gate having a first input terminal that receives the first clock signal and a second input terminal connected to the output terminal of the first latch for receiving the first output signal, wherein the first logic gate outputs the first clock signal based on the first output signal;

a second input stage for outputting a second clock signal, wherein the second input state includes,

a second flip-flop having an input terminal connected to the inverting output terminal of the first latch for receiving the inverted first output signal, a clock input terminal for receiving the second clock signal, and a reset input terminal for receiving an inverted select signal, wherein the second flip-flop generates a second enable signal at an output terminal thereof;

a second latch having an input terminal connected to the output terminal of the second flip-flop for receiving the second enable signal, a clock input terminal for receiving the second clock signal, an output terminal for providing a second output signal, and an inverting output terminal connected to the input terminal of the first flip-flop for providing an inverted second output signal to the input terminal of the first flip-flop; and

a second logic gate having a first input terminal that receives the second clock signal and a second input terminal connected to the output terminal of the second latch for receiving the second output signal, wherein the second logic gate outputs the second clock signal based on the second output signal; and

a third logic gate connected to the first and second logic gates for outputting at least one of the first and second clock signals.

2. The clock multiplexer of claim 1 , wherein the first and second logic gates comprise AND gates.

3. The clock multiplexer of claim 1 , wherein the third logic gate is an OR gate.

4. The clock multiplexer of claim 1 , wherein the first and second flip-flops comprise D type flip-flop.

5. The clock multiplexer of claim 1 , wherein the first and second latches comprise a D type latches.

6. The clock multiplexer of claim 1 , wherein the first and second clock signals are asynchronous.

7. A system for outputting first and second clock signals, comprising:

a first input stage for outputting the first clock signal based on a first output signal, the first input state including,

a first flip-flop having an input terminal for receiving an inverted second output signal, a clock terminal for receiving the first clock signal, and a reset terminal for receiving a select signal, wherein the first flip-flop generates a first enable signal at an output terminal thereof;

a first latch having an input terminal connected to the output terminal of the first flip-flop for receiving the first enable signal, and a clock terminal for receiving the first clock signal, wherein the first latch generates the first output signal at an output terminal thereof and an inverted first output signal at an inverting output terminal thereof; and

a first logic gate having a first input terminal that receives the first clock signal and a second input terminal connected to the output terminal of the first latch for receiving the first output signal, wherein the first logic gate outputs the first clock signal based on the first output signal;

a second input stage for outputting the second clock signal based on a second output signal, the second input stage including,

a second flip-flop having an input terminal connected to the inverting output terminal of the first latch for receiving the inverted first output signal, a clock terminal for receiving the second clock signal, and a reset terminal for receiving an inverted select signal, wherein the second flip-flop generates a second enable signal at an output terminal thereof;

a second latch having an input terminal connected to the output terminal of the second flip-flop for receiving the second enable signal, a clock terminal for receiving the second clock signal, and an inverting output terminal connected to the input terminal of the first flip-flop, wherein the second latch generates the second output signal at an output terminal and the inverted second output signal at the inverting output terminal thereof; and

a second logic gate having a first input terminal for receiving the second clock signal and a second input terminal connected to the output terminal of the second latch for receiving the second output signal, wherein the second logic gate outputs the second clock signal based on the second output signal; and

a third logic gate connected to the first and second logic gates for outputting at least one of the first and second clock signals.

8. The system of claim 7 , wherein the first and second logic gates comprise AND gates.

9. The system of claim 7 , wherein the third logic gate is an OR gate.

10. The system of claim 7 , wherein the first and second flip-flops comprise D type flip-flops.

11. The system of claim 7 , wherein the first and second latches comprise D type latches.

12. The system of claim 7 , wherein the first and second clock signals are asynchronous.

Assignments (20)