IP Library Granted Patent US 8,975,143
Granted Patent B2
US 8,975,143 · App. 13/872,643 · Granted Mar 10, 2015

Selective gate oxide properties adjustment using fluorine

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Quick Facts
Patent No.
US 8,975,143
App. No.
13/872,643
Granted
Mar 10, 2015
Kind
B2
Abstract

Fluorine is located in selective portions of a gate oxide to adjust characteristics of the gate oxide. In some embodiments, the fluorine promotes oxidation which increases the thickness of the selective portion of the gate oxide. In some embodiments, the fluorine lowers the dielectric constant of the oxide at the selective portion. In some examples, having fluorine at selective portions of a select gate oxide of a non volatile memory may reduce program disturb of the memory.

Claims (19)

1. A method for forming a device, comprising:

forming an oxide layer on a substrate including a semiconductor material;

forming a gate layer over the oxide layer;

patterning the gate layer and the oxide layer to form a gate electrode over a gate oxide;

performing an angled implant of fluorine into locations of the device such that the gate oxide has an edge portion between the gate electrode and the substrate with a first concentration of fluorine and a non-edge portion between the gate electrode and the substrate with a second concentration of fluorine that is different than the first concentration;

forming a trench in the substrate; and

filling the trench with isolation material, wherein the performing the angled implant is performed after the forming the isolation trench and before the filling the trench, wherein the performing the angled implant implants fluorine into sidewalls of the trench.

2. The method of claim 1 , wherein the forming the oxide layer, the forming the gate layer, and the patterning the gate layer and the oxide layer are performed after the performing the angled implant, and wherein the edge portion of the gate oxide is closer to the trench than is the non-edge portion of the gate oxide.

3. The method of claim 1 , wherein the performing the angled implant is performed after patterning the gate layer and the oxide layer to define at least one side wall of the gate electrode, wherein the performing the angled implant implants fluorine into the gate oxide and into the substrate below the gate oxide.

4. The method of claim 3 , wherein the gate electrode is further characterized as a select gate of a non-volatile memory cell, and the method further comprises:

after the performing the angled implant, forming a charge storage layer overlapping a sidewall of the select gate, and forming a control gate over the charge storage layer.

5. The method of claim 1 wherein the performing an angled implant of fluorine into locations of the device include implanting fluorine into a region of the substrate, wherein the method includes oxidizing at least a portion of the region of the substrate to increase a thickness of the gate oxide.

6. A method for forming a device, comprising:

forming a trench in a substrate including a semiconductor material;

performing an angled implant to implant fluorine into sidewalls of the trench;

filling the trench with isolation material;

forming an oxide layer on the substrate adjacent the trench;

forming a gate layer over the oxide layer; and

patterning the gate layer and the oxide layer to form a gate electrode over a gate oxide, wherein the gate oxide has an edge portion between the gate electrode and the substrate with a first concentration of fluorine and a non-edge portion between the gate electrode and the substrate with a second concentration of fluorine, the first concentration is at least 10 times greater than the second concentration.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0804 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0819 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0844 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 031248/0750 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0510 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2013
From: MIN, BYOUNG W.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030308/0959 →