Standard cell for semiconductor device
View Patent ↗A standard cell for a semiconductor device has first and second opposing boundaries and third and fourth opposite boundaries, and includes first and second active regions formed in a semiconductor substrate. The first and second active regions are a first predetermined distance (a) from the first and second boundaries, respectively. A gate electrode is formed over the first and second active regions. First and second dummy diffusions layers are formed along the third boundary and are the first predetermined distance (a) from the first and second boundaries and a second predetermined distance (b) from the first and second active regions, respectively. Third and fourth dummy diffusions layers are formed along the fourth boundary and are the first predetermined distance (a) from the first and second boundaries and a third predetermined distance (b′) from the first and second active regions, respectively.
1. A semiconductor device, comprising:
a rectangular standard cell defined in a semiconductor substrate and having first, second, third, and fourth boundaries, wherein the first and second boundaries are on opposite ends of the standard cell, and wherein the third and fourth boundaries are on opposite ends of the standard cell, the standard cell comprising:
a plurality of active regions including first and second active regions formed in the semiconductor substrate, and having a first spacing distance (a) from the first and second boundaries, respectively;
at least one gate electrode strip formed over the first and second active regions;
first and second dummy diffusion layers formed in the semiconductor substrate, wherein the first and second dummy diffusion layers extend along the third boundary and have the first spacing distance (a) from the first and second boundaries and a second spacing distance (b) from the first and second active regions, respectively; and
third and fourth dummy diffusion layers formed in the semiconductor substrate, wherein the third and fourth dummy diffusion layers extend along the fourth boundary and have the first spacing distance (a) from the first and second boundaries and a third spacing distance (b′) from the first and second active regions, respectively.
2. The semiconductor device of claim 1 , further comprising a shallow trench isolation (STI) region filled between the first active region and the first and third dummy diffusion layers, and between the second active region and the second and fourth dummy diffusion layers.
3. The semiconductor device of claim 1 , wherein the first and second dummy diffusion layers have a width that is symmetrical about the third boundary.
4. The semiconductor device of claim 1 , wherein the third and fourth dummy diffusion layers have a width that is symmetrical about the fourth boundary.
5. The semiconductor device of claim 1 , wherein the first and second active regions have opposite conductivities.
6. The semiconductor device of claim 5 , wherein the at least one gate electrode strip and the first active region form a first metal oxide semiconductor (MOS) device and the at least one gate electrode strip and the second active region form a second MOS device.
7. The semiconductor device of claim 6 , wherein the first and second MOS devices each include at least one of a p-type MOS (PMOS) device and a n-type MOS (NMOS) device.
8. A semiconductor device, comprising:
a rectangular standard cell defined in a semiconductor substrate and having first, second, third, and fourth boundaries, wherein the first and second boundaries are on opposite ends of the standard cell, and the third and fourth boundaries are on opposite ends of the standard cell, the standard cell comprising:
a plurality of pairs of active regions including first and second pairs of active regions formed in the semiconductor substrate, wherein each pair of active regions includes first and second active regions having a first spacing distance (a) from the first and second boundaries, respectively;
at least one gate electrode strip formed over each of the first and second pairs of active regions;
first and second dummy diffusion layers formed in the semiconductor substrate, wherein the first and second dummy diffusion layers extend along the third boundary and have the first spacing distance (a) from the first and second boundaries, respectively, and a second spacing distance (b) from the first pair of active regions; and
third and fourth dummy diffusion layers formed in the semiconductor substrate, wherein the third and fourth dummy diffusion layers extend along the fourth boundary and have the first spacing distance (a) from the first and second boundaries, respectively, and a third spacing distance (b′) from the second pair of active regions.
9. The semiconductor device of claim 8 , further comprising a shallow trench isolation (STI) region filled between the first pair of active regions and the first and third dummy diffusion layers, and between the second pair of active regions and the second and fourth dummy diffusion layers.
10. The semiconductor device of claim 8 , wherein the first and second dummy diffusion layers have a width that is symmetrical about the third boundary.
11. The semiconductor device of claim 8 , wherein the third and fourth dummy diffusion layers have a width that is symmetrical about the fourth boundary.
12. The semiconductor device of claim 8 , wherein the first and second active regions have opposite conductivities.
13. The semiconductor device of claim 12 , wherein the at least one gate electrode strip and the first active region form a first metal oxide semiconductor (MOS) device and the at least one gate electrode strip and the second active region form a second MOS device.
14. The semiconductor device of claim 13 , wherein the first and second MOS devices each include at least one of a p-type MOS (PMOS) device and a n-type MOS (NMOS) device.
15. A semiconductor device, comprising:
first and second rectangular standard cells defined in a semiconductor substrate and each having first, second, third, and fourth boundaries, wherein the first and second boundaries are on opposite ends of each of the first and second standard cells, and wherein the third and fourth boundaries are on opposite ends of each of the first and second standard cells, and wherein the first and second standard cells are abutted such that fourth boundary of the first standard cell overlaps the third boundary of the second standard cell to form an overlapping boundary, and wherein the first standard cell comprises:
first and second active regions formed in the semiconductor substrate and having a first spacing distance (a) from the first and second boundaries, respectively;
a first gate electrode strip formed over the first and second active regions;
first and second dummy diffusion layers formed in the semiconductor substrate, wherein the first and second dummy diffusion layers extend along the third boundary and have the first spacing distance (a) from the first and second boundaries and a second spacing distance (b) from the first and second active regions, respectively; and
third and fourth dummy diffusion layers formed in the semiconductor substrate, wherein the third and fourth dummy diffusion layers extend along the overlapping boundary and have the first spacing distance (a) from the first and second boundaries, and a third spacing distance (b′) from the first and second active regions, respectively,
and wherein the second standard cell comprises:
third and fourth active regions formed in the semiconductor substrate and having the first spacing distance (a) from the first and second boundaries and a fourth spacing distance (c) from the third and fourth dummy diffusion layers, respectively;
a second gate electrode strip formed over the third and fourth active regions; and
fifth and sixth dummy diffusion layers formed in the semiconductor substrate, wherein the fifth and sixth dummy diffusion layers extend along the fourth boundary and have the first spacing distance (a) from the first and second boundaries and a fifth spacing distance (c′) from the third and fourth active regions.
16. The semiconductor device of claim 15 , further comprising a shallow trench isolation (STI) region filled between the first active region and the first and third dummy diffusion layers, the second active region and the second and fourth dummy diffusion layers, the third active region and the third and fifth dummy diffusion layers, and the fourth active region and the fourth and sixth dummy diffusion layers.
17. The semiconductor device of claim 15 , wherein the first and second active regions and the third and fourth active regions each have opposite conductivities.
18. The semiconductor device of claim 17 , wherein the first gate electrode strip and the first and second active regions form first and second metal oxide semiconductor (MOS) devices and the second gate electrode strip and the third and fourth active regions form third and fourth MOS devices.
19. The semiconductor device of claim 18 , wherein the first, second, third and fourth MOS devices each include at least one of a p-type MOS (PMOS) device and a n-type MOS (NMOS) device.