Method for detecting bank collision at a memory and device therefor
View Patent ↗A pipeline circuit determines a first effective address based a sum of a first value and a second value. The first effective address is based upon an actual value of a carry-in into a bit-wise region of the first and second values. The bit-wise region includes a predefined internal region of bits of the first and second values. The pipeline circuit also determines a second effective address based a sum of a third value and a fourth value. A collision detector circuit receives bits from the bit-wise region of each of the four values and determines a plurality of speculative results based upon the bits of the bit-wise regions and based upon a plurality of speculative carry-in values. A collision indicator is asserted based on at least one result of the plurality of speculative results, and the actual values of the first and second carry-in.
1. A method comprising:
determining at a pipeline circuit, a first effective address based a sum of a first value and a second value, the first effective address based upon an actual value of a first carry-in into a bit-wise region of the first and second values, wherein the bit-wise region includes a predefined internal region of bits of the first and second values;
determining at the pipeline circuit, a second effective address based a sum of a third value and a fourth value, the second effective address based upon an actual value of a second carry-in into the bit-wise region of the third and fourth values;
receiving, at a collision detector circuit, corresponding bits from the bit-wise region of each of the first, second, third, and fourth values;
determining a plurality of speculative results based upon the bits of the bit-wise regions of the first, second, third, and fourth values and based upon a plurality of speculative carry-in values, the speculative carry-in values being speculative of the actual first and second carry-in values; and
asserting an indicator to indicate a memory access collision, the indicator based on at least one result of the plurality of speculative results, and in response to receiving the actual value of the first carry-in and the actual value of the second carry-in from the pipeline circuit.
2. The method of claim 1 , wherein determining the plurality of speculative results further comprises:
determining a first speculative result based on values of bits of the bit-wise region of the first value, the second value, the third value, the fourth value, and a first speculative value of the first carry-in and a first speculative value of the second carry-in;
determining a second speculative result based on values of bits of the bit-wise region of the first value, the second value, the third value, the fourth value, and the first speculative value of the first carry-in and a second speculative value of the second carry-in;
determining a third speculative result based on values of bits of the bit-wise region of the first value, the second value, the third value, the fourth value, and a second speculative value of the first carry-in and the first speculative value of the second carry-in; and
determining a fourth speculative result based on values of bits of the bit-wise region of the first value, the second value, the third value, the fourth value, and the second speculative value of the first carry-in and the second speculative value of the second carry-in into the bit-wise region.
3. The method of claim 1 , wherein determining the plurality of speculative results further comprises:
determining a first speculative result based on values of bits of the bit-wise region of the first value, values of bits of the bit-wise region of the second value, and a first speculative value of the first carry-in into the bit-wise region;
determining a second speculative result based on the values of bits of the bit-wise region of the first value, the values of bits of the bit-wise region of the second value, and a second speculative value of the first carry-in into the bit-wise region;
determining a third speculative result based on values of bits of the bit-wise region of a third value, values of bits of the bit-wise region of a fourth value, and a first speculative value of a second carry-in into the corresponding bit-wise region; and
determining a fourth speculative result based on the values of bits of the bit-wise region of the third value, the values of bits of the bit-wise region of the fourth value, and a second speculative value of the second carry-in into the corresponding bit-wise region.
4. The method of claim 1 , wherein asserting the indicator further comprises determining values at bits of the bit-wise region of the sum of the first value and the second value are equal to values of corresponding bits of the bit-wise region of the sum of the third value and the fourth value.
5. The method of claim 1 , wherein asserting the indicator further comprises determining two memory access requests will collide.
6. The method of claim 1 , wherein determining the first speculative result further comprises determining a value of a first speculative carry-out of a first bit position of the bit-wise region.
7. The method of claim 1 , wherein the first value represents a base address and the second value represents an address offset, the first effective address associated with a first memory access request of a first program thread and corresponding to a location at a memory device, and wherein the third value represents a base address and the fourth value represents an address offset, the second effective address associated with a second memory access request of a second program thread and corresponding to another location at the memory device.
8. The method of claim 1 , wherein the first, second, third, and fourth speculative results are determined concurrently with a determination of the actual values of the first carry-in and the second carry-in.
9. The method of claim 1 , wherein the actual value of the first carry-in is determined during a calculation of the first effective address and the actual value of the second carry-in is determined during a calculation of the second effective address.
10. A data processing device comprising:
a pipeline circuit to:
determine a first effective address based a sum of a first value and a second value, the first effective address based upon an actual value of a first carry-in into a bit-wise region of the first and second values, wherein the bit-wise region includes a predefined internal region of bits of the first and second values; and
determine a second effective address based a sum of a third value and a fourth value, the second effective address based upon an actual value of a second carry-in into the bit-wise region of the third and fourth values; and
a collision detector circuit coupled to the pipeline circuit to:
receive corresponding bits from the bit-wise region of each of the first, second, third, and fourth values;
determine a plurality of speculative results based upon the bits of the bit-wise regions of the first, second, third, and fourth values and based upon a plurality of speculative carry-in values, the speculative carry-in values being speculative of the actual first and second carry-in values; and
assert an indicator to indicate a memory access collision, the indicator based on at least one result of the plurality of speculative results, and in response to receiving the actual value of the first carry-in and the actual value of the second carry-in from the pipeline circuit.
11. The data processing device of claim 10 , wherein determining the plurality of speculative results further comprises:
determining a first speculative result based on values of bits of the bit-wise region of the first value, the second value, the third value, the fourth value, and a first speculative value of the first carry-in and a first speculative value of the second carry-in;
determining a second speculative result based on values of bits of the bit-wise region of the first value, the second value, the third value, the fourth value, and the first speculative value of the first carry-in and a second speculative value of the second carry-in;
determining a third speculative result based on values of bits of the bit-wise region of the first value, the second value, the third value, the fourth value, and a second speculative value of the first carry-in and the first speculative value of the second carry-in; and
determining a fourth speculative result based on values of bits of the bit-wise region of the first value, the second value, the third value, the fourth value, and the second speculative value of the first carry-in and the second speculative value of the second carry-in into the bit-wise region.
12. The data processing device of claim 10 , wherein determining the plurality of speculative results further comprises:
determining a first speculative result based on values of bits of the bit-wise region of the first value, values of bits of the bit-wise region of the second value, and a first speculative value of the first carry-in into the bit-wise region;
determining a second speculative result based on the values of bits of the bit-wise region of the first value, the values of bits of the bit-wise region of the second value, and a second speculative value of the first carry-in into the bit-wise region;
determining a third speculative result based on values of bits of the bit-wise region of a third value, values of bits of the bit-wise region of a fourth value, and a first speculative value of a second carry-in into the corresponding bit-wise region; and
determining a fourth speculative result based on the values of bits of the bit-wise region of the third value, the values of bits of the bit-wise region of the fourth value, and a second speculative value of the second carry-in into the corresponding bit-wise region.
13. The data processing device of claim 10 , wherein asserting the indicator further comprises determining values at bits of the bit-wise region of the sum of the first value and the second value are equal to values of corresponding bits of the bit-wise region of the sum of the third value and the fourth value.
14. The data processing device of claim 10 , wherein asserting the indicator further comprises determining two memory access requests will collide.
15. The data processing device of claim 10 , wherein determining the first speculative result further comprises determining a value of a first speculative carry-out of a first bit position of the bit-wise region.
16. The data processing device of claim 10 , wherein the first value represents a base address and the second value represents an address offset, the first effective address associated with a first memory access request of a first program thread and corresponding to a location at a memory device, and wherein the third value represents a base address and the fourth value represents an address offset, the second effective address associated with a second memory access request of a second program thread and corresponding to another location at the memory device.
17. The data processing device of claim 10 , wherein the first, second, third, and fourth speculative results are determined concurrently with a determination of the actual values of the first carry-in and the second carry-in.
18. A method comprising:
determining at a first circuit a first sum of a first value and a second value, the first sum based upon an actual value of a first carry-in into a bit-wise region of the first and second values, wherein the bit-wise region includes a predefined internal region of bits of the first and second values;
determining at the first circuit a second sum of a third value and a fourth value, the second sum based upon an actual value of a second carry-in into the bit-wise region of the third and fourth values;
receiving, at a second circuit, corresponding bits from the bit-wise region of each of the first, second, third, and fourth values;
determining a plurality of speculative results based upon the bits of the bit-wise regions of the first, second, third, and fourth values and based upon a plurality of speculative carry-in values, the speculative carry-in values being speculative of the actual first and second carry-in values; and
assert an indicator indicating values of bits of the bit-wise region of a sum of the first value and the second value are equal to values of corresponding bits of the bit-wise region of a sum of the third value and the fourth value based on the first speculative result, the second speculative result, the third speculative result, and the fourth speculative result, in response to receiving the actual value of the first carry-in and the actual value of the second carry-in.
19. The method of claim 18 , wherein determining the plurality of speculative results further comprises:
determining a first speculative result based on values of bits of the bit-wise region of the first value, the second value, the third value, the fourth value, and a first speculative value of the first carry-in and a first speculative value of the second carry-in;
determining a second speculative result based on values of bits of the bit-wise region of the first value, the second value, the third value, the fourth value, and the first speculative value of the first carry-in and a second speculative value of the second carry-in;
determining a third speculative result based on values of bits of the bit-wise region of the first value, the second value, the third value, the fourth value, and a second speculative value of the first carry-in and the first speculative value of the second carry-in; and
determining a fourth speculative result based on values of bits of the bit-wise region of the first value, the second value, the third value, the fourth value, and the second speculative value of the first carry-in and the second speculative value of the second carry-in into the bit-wise region.
20. The method of claim 18 , wherein the first value represents a base address and the second value represents an address offset, the first sum to provide an effective address associated with a first memory access request of a first program thread and corresponding to a location at a memory device, and wherein the third value represents a base address and the fourth value represents an address offset, the second sum to provide an effective address associated with a second memory access request of a second program thread and corresponding to another location at the memory device.