Data retention flip-flop
View Patent ↗An integrated circuit (IC) includes a flip-flop that stores data when the IC is in built-in self-test (BIST) mode. The flip-flop includes a master latch connected to a slave latch, which in turn is connected to a data retention latch. A control circuit is connected to the flip-flop. During normal operation, the master latch receives a data input signal, which is transmitted through the slave latch to another flip-flop of the IC. When the control circuit initiates BIST (scan testing), data stored in the slave latch is transferred to the data retention latch. Upon completion of BIST, the data stored in the retention latch is used to restore the flip-flop to its original state.
1. A data retention flip-flop, comprising:
a first multiplexer having a first input terminal that receives a data input signal, a second input terminal that receives a scan input signal, and a select terminal that receives a test enable signal, wherein the first multiplexer outputs the data input signal at an output terminal thereof in a normal operation mode of the data retention flip-flop;
a master latch having a data input terminal connected to the output terminal of the first multiplexer for receiving the data input signal, and a clock input terminal that receives a clock signal, wherein the master latch outputs the data input signal at an output terminal thereof at a first edge of the clock signal in the normal operation mode;
a slave latch having a data input terminal connected to the output terminal of the master latch for receiving the data input signal, and a clock input terminal that receives the clock signal, wherein the slave latch outputs the data input signal at an output terminal thereof at the first edge of the clock signal in the normal operation mode;
a data retention latch having a data input terminal connected to the output terminal of the slave latch for receiving the data input signal and a clock input terminal that receives an isolation (ISO) signal, wherein the ISO signal is asserted when the data retention flip-flop transitions from the normal operation mode to a scan testing mode such that the data retention latch stores the data input signal during the scan testing mode; and
a second multiplexer having a first input terminal connected to an output terminal of the data retention latch for receiving the stored data input signal, a second input terminal connected to the output terminal of the slave latch for receiving the data input signal, and a select terminal that receives a propagation (PROP) signal, wherein the second multiplexer outputs the stored data input signal when the data retention flip-flop transitions from the scan testing mode to a reload mode, and outputs the data input signal during the normal operation mode.
2. The data retention flip-flop of claim 1 , wherein when the ISO signal is de-asserted, the data retention flip-flop transitions from the reload mode to the normal operation mode.
3. The data retention flip-flop of claim 1 , wherein the PROP signal is de-asserted during the scan testing and normal operation modes and asserted when the data retention flip-flop transitions from the scan testing mode to the reload mode.
4. The data retention flip-flop of claim 1 , wherein the PROP signal is de-asserted after the stored data input signal is output by the second multiplexer.
5. The data retention flip-flop of claim 1 , wherein the test enable signal is asserted in the scan testing mode and de-asserted in the normal operation mode.
6. The data retention flip-flop of claim 1 , wherein the data retention flip-flop receives the clock signal from an external clock generator.
7. The data retention flip-flop of claim 1 , wherein the data retention flip-flop receives the ISO and PROP signals from an external control circuit.
8. An integrated circuit, comprising:
a plurality of flip-flops, wherein each flip-flop includes:
a first multiplexer having a first input terminal that receives a data input signal, a second input terminal that receives a scan input signal, and a select terminal that receives a test enable signal, wherein the first multiplexer outputs the data input signal at an output terminal thereof during a normal operation mode of the integrated circuit;
a master latch having a data input terminal connected to the output terminal of the first multiplexer for receiving the data input signal, and a clock input terminal that receives a clock signal, wherein the master latch outputs the data input signal at an output terminal thereof at a first edge of the clock signal in the normal operation mode;
a slave latch having a data input terminal connected to the output terminal of the master latch for receiving the data input signal, and a clock input terminal that receives the clock signal, wherein the slave latch outputs the data input signal at an output terminal thereof at the first edge of the clock signal in the normal operation mode;
a data retention latch having a data input terminal connected to the output terminal of the slave latch for receiving the data input signal and a clock input terminal that receives an isolation (ISO) signal, wherein the ISO signal is asserted when the integrated circuit transitions from the normal operation mode to a scan testing mode such that the data retention latch stores the data input signal in the scan testing mode; and
a second multiplexer having a first input terminal connected to an output terminal of the data retention latch for receiving the stored data input signal, a second input terminal connected to the output terminal of the slave latch for receiving the data input signal, and a select terminal that receives a propagation (PROP) signal, wherein the second multiplexer outputs the stored data input signal when the integrated circuit transitions from the scan testing mode to a reload mode, and outputs the data input signal during the normal operation mode.
9. The integrated circuit of claim 8 , wherein the ISO signal is de-asserted when the integrated circuit transitions from the reload mode to the normal operation mode.
10. The integrated circuit of claim 8 , wherein the PROP signal is de-asserted during the scan testing and normal operation modes and asserted when the integrated circuit transitions from the scan testing mode to the reload mode.
11. The integrated circuit of claim 8 , wherein the PROP signal is de-asserted after the stored data input signal is transmitted by the second multiplexer.
12. The integrated circuit of claim 8 , wherein the test enable signal is asserted in the scan testing mode and de-asserted in the normal operation mode.
13. The integrated circuit of claim 8 , further comprising a clock generator for generating the clock signal.
14. The integrated circuit of claim 13 , further comprising a control circuit for generating the ISO and PROP signals.
15. An integrated circuit, comprising:
a clock generator for generating a clock signal;
a control circuit for generating an isolation (ISO) signal and a propagation (PROP) signal; and
a plurality of circuit modules, wherein each circuit module includes a plurality of flip-flops, and wherein each flip-flop includes:
a first multiplexer having a first input terminal that receives a data input signal, a second input terminal that receives a scan input signal, and a select terminal that receives a test enable signal, wherein the first multiplexer outputs the data input signal at an output terminal thereof during a normal operation mode of the integrated circuit;
a master latch having an input terminal connected to the output terminal of the first multiplexer for receiving the data input signal, and a clock input terminal connected to the clock generator for receiving the clock signal, wherein the master latch outputs the data input signal at an output terminal thereof at a first edge of the clock signal in the normal operation mode;
a slave latch having an input terminal connected to the output terminal of the master latch for receiving the data input signal, and a clock input terminal connected to the clock generator for receiving the clock signal, wherein the slave latch outputs the data input signal at an output terminal thereof at the first edge of the clock signal in the normal operation mode;
a data retention latch having an input terminal connected to the output terminal of the slave latch for receiving the data input signal, and a clock input terminal connected to the control circuit for receiving the ISO signal, wherein the ISO signal is asserted when the integrated circuit transitions from the normal operation mode to a scan testing mode such that the data retention latch stores the data input signal during the scan testing mode; and
a second multiplexer having a first input terminal connected to an output terminal of the data retention latch for receiving the stored data input signal, a second input terminal connected to the output terminal of the slave latch for receiving the data input signal, and a select terminal connected to the control circuit for receiving the PROP signal, wherein the second multiplexer outputs the stored data input signal when the integrated circuit transitions from the scan testing mode to a reload mode, and outputs the data input signal in the normal operation mode.
16. The integrated circuit of claim 15 , wherein the control circuit de-asserts the ISO signal when the integrated circuit transitions from the reload mode to the normal operation mode.
17. The integrated circuit of claim 15 , wherein the control circuit de-asserts the PROP signal in the scan testing and normal operation modes and asserts the PROP signal when the integrated circuit transitions from the scan testing mode to the reload mode.
18. The integrated circuit of claim 17 , wherein the control circuit de-asserts the PROP signal after the stored data input signal is output by the second multiplexer.
19. The integrated circuit of claim 15 , wherein the test enable signal is asserted in the scan testing mode of the integrated circuit and de-asserted during the normal operation mode.