METHODS AND STRUCTURES FOR SPLIT GATE MEMORY
A method of making a non-volatile memory (NVM) cell using a substrate having a top surface of silicon includes forming a select gate stack over the substrate. An oxide layer is grown on the top surface of the substrate. Nanocrystals of silicon are formed on the thermal oxide layer adjacent to a first side the select gate stack. The nanocrystals are partially oxidized to result in partially oxidized nanocrystals and further growing the thermal oxide layer. A control gate is formed over the partially oxidized nanocrystals. A first doped region is formed in the substrate adjacent to a first side of the control gate and a second doped region in the substrate adjacent to a second side of the select gate.
1 . A method of making a non-volatile memory (NVM) cell using a substrate having a top surface of silicon, comprising:
forming a select gate stack over the substrate;
growing a thermal oxide layer on the top surface of the substrate;
forming nanocrystals of silicon on the thermal oxide layer adjacent to a first side of the select gate stack;
partially oxidizing the nanocrystals to result in partially oxidized nanocrystals and further growing the thermal oxide layer;
forming a control gate over the partially oxidized nanocrystals;
forming a first doped region in the substrate adjacent to a first side of the control gate and a second doped region in the substrate adjacent to a second side of the select gate.
2 . The method of claim 1 , wherein the step of forming the select gate stack is further characterized by the select gate stack comprising polysilicon.
3 . The method of claim 2 , wherein the step of growing the thermal oxide layer is further characterizing as growing the thermal oxide on the polysilicon on the first side of the select gate.
4 . The method of claim 3 , wherein the step of forming the nanocrystals is further characterized by forming nanocrystals on the thermal oxide on the first side of the select gate.
5 . The method of claim 4 , further comprising forming sidewall spacers adjacent to the second side of the select gate and the first side of the control gate.
6 . The method of claim 1 , wherein the step of forming the control gate is further characterized by the control gate being deposited directly on the partially oxidized nanocrystals.
7 . The method of claim 6 , wherein the step of forming the control gate is further characterized by the control gate comprising polysilicon.
8 . The method of claim 1 , further comprising depositing a dielectric layer on the partially oxidized nanocrystals prior to forming the control gate, wherein the forming the control gate is further characterized by being over the dielectric layer.
9 . The method of claim 1 , wherein the step of forming the control gate comprises:
depositing a conductive layer over the partially oxidized nanocrystals; and
patterning the conductive layer to form the first side of the control gate and to form a second side of the control gate over the select gate.
10 . The method of claim 1 , wherein,
the step of forming the nanocrystals is further characterized by the nanocrystals having a median original diameter; and
the step of partially oxidizing the nanocrystals results in a reduction from the median original diameter of about one fourth.
11 . The method of claim 1 , wherein the step of forming the nanocrystals is further characterized by the median original diameter being about 16 nanometers.
12 . The method of claim 1 , wherein the step of partially oxidizing the nanocrystals results in sufficient oxide growth that the oxide growth of adjacent nanocrystals merges.
13 . A method of forming a non-volatile memory (NVM) structure on a substrate having a silicon surface, comprising:
growing an oxide layer on the silicon surface;
forming silicon nanocrystals on the oxide layer;
partially growing oxide on the nanocrystals; and
forming a control gate over the oxide.
14 . The method of claim 13 , wherein the forming the control gate is further characterized as the control gate being directly on the oxide.
15 . The method of claim 13 , further comprising forming a dielectric layer on the oxide, wherein the step of forming the control gate is further characterized by the control gate being over the dielectric layer.
16 . The method of claim 13 , further comprising forming a select gate structure of silicon having a first sidewall prior to the step of growing the oxide layer, wherein:
the step of growing the oxide layer is further characterized by growing the oxide layer on the first sidewall of the select gate structure; and
the step of forming the control gate is further characterized by the control gate being adjacent to the first sidewall of the select gate structure.
17 . The method of claim 13 , wherein:
the step of forming the silicon nanocrystals results in a median spacing between adjacent silicon nanocrystals being less than a thickness of the oxide layer; and
the step of partially growing oxide on the nanocrystals results in the median spacing between adjacent nanocrystals being more than a median distance from lowest surface of the silicon nanocrystals to the substrate.
18 . A method of forming a split gate non-volatile memory (NVM) cell structure using a silicon substrate, comprising:
forming a select gate structure comprising polysilicon having a first side;
applying heat and oxygen to form a thermal oxide layer on a surface of the silicon substrate adjacent to the first side of the select gate structure and on the first side of the of the select gate structure;
forming silicon nanocrystals on the thermal oxide layer;
applying heat and oxygen to oxidize a portion of the nanocrystals; and
after oxidizing a portion of the nanocrystals, forming a control gate over the nanocrystals and adjacent to the first side of the select gate structure.
19 . The method of claim 18 , wherein
the forming the silicon nanocrystals results in a median spacing between adjacent nanocrystals that is less than a thickness of the thermal oxide layer; and
the applying heat and oxygen to oxidize a portion of the nanocrystals results in a median height above a top surface of the substrate of the lower surface of the nanocrystals being less than a median spacing of the nanocrystals.
20 . The method of claim 18 , further comprising depositing a dielectric layer over the nanocrystals after applying heat and oxygen to oxidize a portion of the nanocrystals and before forming the control gate.