Granted Patent B2

US 9,135,157 · App. 13/988,366 · Granted Sep 15, 2015

Abstract

Claims (44)

1. An integrated circuit device comprising:

at least one memory element storing a plurality of lines of data; and

at least one prefetching module for prefetching lines of data from the at least one memory element, wherein the prefetching module is configured to:

determine a position of a requested block of data within a respective line of data within the at least one memory element by dividing the line into s sections and determining which section includes the requested block;

determine a number of subsequent lines of data to prefetch, based at least partly on the determined section; and

cause the prefetching of the number of subsequent lines of data from the at least one memory element based thereon.

2. The integrated circuit device of claim 1 wherein the number of subsequent lines of data to prefetch, n, is determined according to n=x+i, where x is a default number of lines to prefetch, and i is an offset value dependent on the determined section of the line of data within which the requested block of data is located.

3. The integrated circuit device of claim 2 , wherein at least one of s, x, and i is a configurable parameter.

4. The integrated circuit device of claim 2 wherein the prefetching module is operably coupled to at least one register configured to store at least one of the parameters n, s, x, and i.

5. The integrated circuit device of claim 2 wherein the prefetching module is further configured to:

determine, if s=2, whether a requested block of data is located within a first half or a second half of the respective line of data within the at least one memory element; and

if it is determined that the requested block of data is located within the first half of the respective line of data, configure the number of subsequent lines of data to prefetch to be n=x; or

if it is determined that the requested block of data is located within the second half of the respective line of data, configure the number of subsequent lines of data to prefetch to be n=x+i.

6. The integrated circuit device of claim 1 further comprising:

a system bus, wherein the prefetching module is further configured to receive a request for the requested block of data via the system bus.

7. The integrated circuit device of claim 6 wherein the prefetching module is further configured to return the requested block of data via the system bus.

8. The integrated circuit of claim 7 wherein the prefetching module is further configured to:

determine a position of the returned block of data within a respective line of data of the at least one memory element;

determine a number of subsequent lines of data to prefetch based at least partly on the determined position of the returned block of data within the respective line of data of the at least one memory element; and

cause the prefetching of the number of successive lines of data to prefetch from the at least one memory element.

9. The integrated circuit device of claim 1 wherein the prefetching module is further configured to determine whether the requested block of data has been prefetched, and if it is determined that the requested block of data has not been prefetched, to cause the requested data to be fetched from the at least one memory element.

10. The integrated circuit device of claim 1 wherein the at least one memory element comprises an on-chip memory element.

11. The integrated circuit device of claim 1 wherein the at least one memory element comprises a Flash memory element.

12. A signal processing system comprising:

at least one memory element storing a plurality of lines of data; and

at least one prefetching module for prefetching lines of data from the at least one memory element, wherein the prefetching module is configured to:

determine a position of a requested block of data within a respective line of data of the at least one memory element by dividing the line into s sections and determining which section includes the requested block;

determine a number of subsequent lines of data to prefetch, based at least partly on the determined section; and

cause the prefetching of the number of subsequent lines of data n from the at least one memory element based thereon.

13. A method for prefetching lines of data from at least one memory element; the method comprising:

determining a position of a requested block of data within a respective line of data of the at least one memory element by dividing the line into s sections and determining which section includes the requested block;

determining a number of subsequent lines of data to prefetch, based at least partly on the determined section; and

causing the prefetching of the number of subsequent lines of data n from the at least one memory element based thereon.

14. The method of claim 13 further comprising:

receiving a request for the requested block of data via a system bus.

15. The method of claim 13 further comprising:

determining whether the requested block of data has been prefetched;

causing the requested block of data to be fetched from the at least one memory element, if the requested block of data has not been prefetched.

16. The method of claim 13 further comprising:

determining the number of subsequent lines of data to prefetch using a sum of a default number of lines to prefetch (x) and an offset value (i) dependent on the determined section of the line of data within which the requested block of data is located.

17. The method of claim 16 further comprising:

determining, if s=2, whether a requested block of data is located within a first half or a second half of the respective line of data;

configuring the number of subsequent lines of data to prefetch to be x, when the requested block of data is located within the first half of the respective line of data; and

configuring the number of subsequent lines of data to prefetch to be x+i, when the requested block of data is located within the second half of the respective line of data.

Assignments (23)