Method and apparatus for managing power in a multi-core processor
View Patent ↗There is provided a method of managing power in a multi-core data processing system having two or more processing cores, comprising determining usage characteristics for the two or more processing cores within the multi-core processing unit, and dependent on the determined usage characteristics, adapting a frequency or voltage supplied to each of the two or more processing cores, and/or adapting enablement signals provided to each of the two or more processing cores. There is also provided an apparatus for carrying out the disclosed method.
1. A method of managing power in a multi-core data processing system having a plurality of processing cores, comprising:
determining a first performance status and a first leakage status for a first processing core of the plurality of processing cores;
setting a first performance setting for the first processing core to a high-performance state in response to the first performance status comprising a low-performance state and the first leakage status comprising a high-leakage state, wherein the high-leakage state is higher than a low-leakage state;
determining a second leakage status for a second processing core of the plurality of processing cores;
determining a load uniformity status for a load operating on the first processing core and the second processing core; and
in response to the first leakage status comprising the high-leakage state, the second leakage status comprising the high-leakage state, and the load uniformity status comprising a non-uniform state:
setting the first performance setting to the high-performance state; and
setting an enablement setting for the second processing core to a disabled state.
2. The method of claim 1 , further comprising:
setting the enablement setting to an enabled state in response to the first performance status comprising the low-performance state and the leakage status comprising the low-leakage state.
3. The method of claim 1 , further comprising:
determining a second performance status for the second processing core; and
setting the enablement setting to the disabled state in further response to the first performance status comprising the high-performance state and the second performance status comprising the high-performance state.
4. The method of claim 3 , further comprising:
determining a first junction-temperature status for the first processing core; and
in response to the first leakage status comprising the low-leakage state and the first junction-temperature status comprising a high-junction-temperature state:
setting the first performance setting to the low-performance state; and
setting an enablement setting for a second processing core of the plurality of processing cores to an enabled state.
5. The method of claim 4 , further comprising:
determining a second junction-temperature status for a second processing core of the plurality of processing cores;
determining a load uniformity status for a load operating on the first processing core and the second processing core; and
in response to the load uniformity status comprising a uniform state, and one of the first junction-temperature status and the second junction-temperature status comprising the high-junction-temperature state:
setting the first performance setting to the low-performance state; and
setting a second performance setting of the second processing core to the low-performance state.
6. A method of managing power in a multi-core data processing system having a plurality of processing cores, comprising:
determining a first leakage status for a first processing core of the plurality of processing cores;
determining a second leakage status for a second processing core of the plurality of processing cores;
determining a load uniformity status for a load operating on the first processing core and the second processing core; and
in response to the first leakage status comprising a high-leakage state, the second leakage status comprising the high-leakage state, and the load uniformity status comprising a non-uniform state:
setting a first enablement setting for the first processing core to an enabled state;
setting a first performance setting for the first processing core to a high-performance state and
setting a second enablement setting for the second processing core to a disabled state.
7. The method of claim 6 , further comprising:
in response to the load uniformity status comprising a uniform state;
setting the first performance setting to a low-performance state; and
setting a second performance setting for the second processing core to the low-performance state.
8. The method of claim 6 , further comprising:
determining a first performance status and a first junction-temperature status for the first processor core;
determining a second performance status for the second processor core; and
in response to the first performance status comprising a high performance state, the second performance status comprising the high performance state, the load uniformity status comprising a uniform state, and the first junction-temperature status comprising a high-junction-temperature state;
setting the first performance setting to a low-performance state; and
setting a second performance setting for the second processing core to the low-performance state.