Four port memory with multiple cores
View Patent ↗A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core is in the center hole coupled to the first port of each of the first, second, third, and fourth blocks. A second core is in the center hole coupled to the second port of each of the first, second, third, and fourth blocks. A third core is in the center hole coupled to the third port of each of the first, second, third, and fourth blocks. A fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks.
1. A memory cluster, comprising:
a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port;
a first core in the center hole coupled to the first port of each of the first, second, third, and fourth blocks;
a second core in the center hole coupled to the second port of each of the first, second, third, and fourth blocks;
a third core in the center hole coupled to the third port of each of the first, second, third, and fourth blocks; and
a fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks.
2. The memory cluster of claim 1 , further comprising:
a first vertical bus between the first and second blocks extending from the center hole to a first location of a perimeter of the memory cluster, wherein the first block comprises word lines running parallel with the first vertical bus.
3. The memory cluster of claim 2 , further comprising:
a second vertical bus between the third and fourth blocks extending from the center hole to a second location of the perimeter of the memory cluster.
4. The memory cluster of claim 3 , further comprising:
a first horizontal bus between the first and fourth blocks extending from the center hole to a third location of the perimeter of the memory cluster, wherein the first block comprises bit lines running parallel with the first horizontal bus; and
a second horizontal bus between the second and third blocks extending from the center hole to a fourth location of the perimeter of the memory cluster.
5. The memory cluster of claim 2 , further comprising a first switch coupled to the first vertical bus at the first location of the perimeter.
6. The memory cluster of claim 5 , further comprising a second switch coupled between the first core and the first vertical bus at the center hole.
7. A system comprising the memory cluster of claim 2 , the system further comprising a second memory cluster coupled to the first vertical bus.
8. The system of claim 7 , wherein the first vertical bus is used to run memory accesses by the second memory cluster on the first block.
9. The system of claim 7 , wherein the first vertical bus is used by the second memory cluster to run processor accesses using the first core.
10. An array of memory clusters including the memory cluster of claim 1 , wherein each memory cluster comprises four blocks that are each four-port and a center hole having four cores wherein the memory clusters are interconnected by a plurality of vertical and horizontal buses.
11. A method, comprising:
providing a memory cluster having four cores and four blocks, wherein each of the four blocks is four-port; and
performing accesses simultaneously to the four blocks from four cores located in a center hole defined by the four blocks.
12. The method of claim 11 , further comprising:
performing a processor access to a selected core of the four cores, initiated externally from the memory cluster, through a bus running from a perimeter of the memory cluster to the center hole.
13. The method of claim 11 , performing a memory access to a selected core of the four cores, initiated externally from the memory cluster, through a bus running from a perimeter of the memory cluster to the center hole.
14. A cluster, comprising:
a memory comprising a first block, a second block, a third block, and a fourth block arranged to have center hole, where the first, second, third, and fourth blocks have a first port, a second port, a third port, and a fourth port; and
a first core coupled to the first port, a second core coupled to the second port, a third core coupled to the third port, and a fourth core coupled to the fourth port, wherein the first, second, third, and fourth cores are in the center hole.
15. The cluster of claim 14 , wherein the first, second, third, and fourth cores can perform accesses simultaneously to the memory.
16. The cluster of claim 14 , wherein the memory comprises:
a plurality of word lines running vertically;
a first vertical bus and a second vertical bus running parallel with the plurality of word lines;
wherein the first, second, third, and fourth cores are coupled to the first and second vertical buses.
17. The cluster of claim 16 , further comprising:
a plurality of bit lines running horizontally; and
a first horizontal bus and a second horizontal bus running parallel with the plurality of bit lines;
wherein the first, second, third, and fourth cores are coupled to the first and second horizontal buses.
18. The cluster of claim 17 , further comprising:
a first switch coupled between the first vertical bus and the first, second, third, and fourth cores at the center hole; and
a second switch coupled to the first vertical bus at a perimeter of the memory.
19. The cluster of claim 18 , further comprising a third switch coupled between the first horizontal bus and the second switch and the first, second, third, and fourth cores at the center hole.
20. A system comprising the cluster of claim 17 wherein the first horizontal bus and the first vertical bus are for running one of a group consisting of a processor access and a memory access.