Method, system, and computer program product
View Patent ↗A method for retrieving trace data from a target device is proposed. The target device comprises a program memory, a processor, a trace unit, and a trace buffer. The processor is operable to retrieve instructions from the program memory and to execute them. The trace buffer may contain trace data generated by the trace unit in response to the processor retrieving or executing instructions from the program memory. One or more patch instructions are written to the program memory. The processor executes said one or more patch instructions. The target device, in response to the processor executing said one or more patch instructions, performs a data transfer operation for copying the trace data from the trace buffer to a second memory outside the target device.
1. A method of retrieving trace data from a target device, the target device comprising:
a program memory,
a processor for retrieving instructions from the program memory and executing them,
a trace unit, and
a trace buffer including trace data generated by the trace unit in response to the processor retrieving or executing instructions from the program memory;
wherein the method comprises:
writing one or more patch instructions to the program memory, the patch instructions comprising at least a first patch instruction;
operating the processor to execute said one or more patch instructions; and
the target device performing a data transfer operation for copying the trace data from the trace buffer to a second memory outside the target device, in response to the processor executing said patch instructions, wherein said operating the processor to execute said one or more patch instructions comprises:
the processor retrieving or executing a triggering instruction;
the trace unit advancing a Trace Write Pointer by a defined increment in response to said retrieving or executing the triggering instruction;
the Trace Write Pointer thus hitting a Trace Event Request address of the trace buffer; and
the trace unit triggering the data transfer operation in response to the Trace Write Pointer hitting the Trace Event Request address.
2. The method as set forth in claim 1 , wherein the processor enters a stop mode prior to said writing.
3. The method as set forth in claim 2 , wherein a debugging interface is used to read data from and write data to the target device while the processor is in the stop mode.
4. The method as set forth in claim 1 , wherein the target device has a program counter indicating a current location in the program memory and the method further comprises
reading the program counter;
and said writing comprises
writing the first patch instruction to a location according to the indicated location.
5. The method as set forth in claim 1 , wherein the target device has a program counter indicating a current location in the program memory and said writing comprises
writing the first patch instruction to a selected location in the program memory;
and the method further comprises
setting the program counter according to the selected location.
6. The method as set forth in claim 1 , wherein triggering the data transfer operation comprises
the trace unit generating an interrupt; and
the processor executing an interrupt service routine in response to the interrupt, the interrupt service routine comprising instructions for performing the data transfer operation.
7. The method as set forth in claim 1 , further comprising, prior to said operating,
setting the trace unit into a Trace Event Request mode; and
setting the Trace Event Request address according to a trace buffer address indicated by the Trace Write Pointer.
8. The method as set forth in claim 1 , wherein the triggering instruction is either the first patch instruction or an instruction referenced by the first patch instruction.
9. The method as set forth in claim 1 , wherein the triggering instruction is a jump to a second instruction or a call of a subroutine.
10. The method as set forth in claim 9 , wherein the second instruction or the subroutine comprises a stop instruction.
11. The method as set forth in claim 1 , wherein said operating comprises
setting the processor into a run mode or into a single-step mode.
12. The method as set forth in claim 1 , further comprising
restoring original instructions in the program memory, wherein the original instructions resided in the program memory prior to the writing the one or more patch instructions to the program memory.
13. A system comprising a host device and a target device, wherein the system is arranged to perform the method as set forth in claim 1 .
14. A non-transitory machine-readable storage medium for enabling a host device to perform the method as set forth in claim 1 .
15. A method of retrieving trace data from a target device, the target device comprising a program memory, a processor for retrieving instructions from the program memory and executing the instructions, a trace unit, and a trace buffer including trace data generated by the trace unit in response to the processor retrieving or executing instructions from the program memory, wherein the method comprises:
writing one or more patch instructions to the program memory, the patch instructions comprising at least a first patch instruction;
operating the processor to execute said one or more patch instructions; and
the target device performing a data transfer operation for copying the trace data from the trace buffer to a second memory outside the target device in response to a trace write pointer hitting a trace event request address, wherein said operating comprises:
the processor retrieving or executing a triggering instruction;
the trace unit advancing a Trace Write Pointer by a defined increment in response to said retrieving or executing the triggering instruction;
the Trace Write Pointer thus hitting a Trace Event Request address of the trace buffer; and
the trace unit triggering the data transfer operation in response to the Trace Write Pointer hitting the Trace Event Request address.
16. The method as set forth in claim 15 , wherein the processor enters a stop mode prior to said writing.
17. The method as set forth in claim 16 , wherein a debugging interface is used to read data from and write data to the target device while the processor is in the stop mode.
18. The method as set forth in claim 15 , wherein the target device has a program counter indicating a current location in the program memory and the method further comprises
reading the program counter;
and said writing comprises
writing the first patch instruction to a location according to the indicated location.
19. The method as set forth in claim 15 , wherein the target device has a program counter indicating a current location in the program memory and said writing comprises
writing the first patch instruction to a selected location in the program memory;
and the method further comprises
setting the program counter according to the selected location.