Multiple data rate memory with read timing information
View Patent ↗A memory includes a memory array, read circuitry, and a strobe generator. The read circuitry is configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock. The strobe generator is configured to provide a strobe signal with the read data, wherein the strobe generator provides the strobe signal in accordance with a second clock. The second clock is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees.
1. A memory comprising:
a memory array;
read circuitry coupled to the memory array and configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock; and
a strobe generator configured to provide a strobe signal with the read data, wherein the strobe generator provides the strobe signal in accordance with a second clock which is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees;
wherein the strobe generator is configured to transition the strobe signal at rising and falling edges of the second clock;
wherein the strobe generator is configured to receive the second clock and an inverse of the second clock, and is configured to transition the strobe signal at zero crossings of the second clock and the inverse of the second clock.
2. A memory comprising:
a memory array;
read circuitry coupled to the memory array and configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock; and
a strobe generator configured to provide a strobe signal with the read data, wherein the strobe generator provides the strobe signal in accordance with a second clock which is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees;
wherein the strobe generator is configured to transition the strobe signal at rising and falling edges of the second clock;
wherein the first clock and the second clock have different frequencies.
3. A memory comprising:
a memory array;
read circuitry coupled to the memory array and configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock; and
a strobe generator configured to provide a strobe signal with the read data, wherein the strobe generator provides the strobe signal in accordance with a second clock which is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees;
wherein the strobe generator is configured to receive a third clock, wherein the third clock is generated from a combination of the first and second clocks, and has a higher frequency than each of the first clock and the second clock.
4. The memory of claim 3 , wherein the read circuitry is configured to provide the read data at a first edge type of the third clock, and the strobe generator is configured to transition the strobe signal at a second edge type, different from the first edge type, of the third clock, wherein each of the first edge type and the second edge type is one of a rising or falling edge.
5. In a memory having a memory array, a method comprising:
receiving a read request; and
in response to the read request:
providing read data from the memory array in accordance with a first clock, and
providing a strobe signal with the read data in accordance with a second clock, wherein the second clock is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees;
wherein providing the read data comprises providing data beats of the read data at rising and falling edges of the first clock;
wherein providing the strobe signal comprises transitioninq the strobe signal between a first level and a second level at rising and falling edges of the second clock; and
wherein providing transitions of the strobe signal at rising and falling edges of the second clock comprises providing transitions of the strobe signal at zero crossings of the second clock and an inverse of the second clock.
6. In a memory having a memory array, a method comprising:
receiving a read request;
in response to the read request:
providing read data from the memory array in accordance with a first clock, and
providing a strobe signal with the read data in accordance with a second clock, wherein the second clock is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees;
combining the first clock and the second clock to generate a third clock which has a higher frequency than each of the first clock and the second clock, wherein:
providing the read data comprises providing data beats of the read data at a first edge type of the third clock; and
providing the strobe signal comprises transitioning the strobe signal between a first level and a second level at a second edge type of the third clock, different from the first edge type, wherein each of the first edge type and the second edge type is one of a rising or falling edge.