IP Library Granted Patent US 8,836,098
Granted Patent B1
US 8,836,098 · App. 13/894,440 · Granted Sep 16, 2014

Surface mount semiconductor device with solder ball reinforcement frame

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,836,098
App. No.
13/894,440
Granted
Sep 16, 2014
Kind
B1
Abstract

A surface mount semiconductor device having external contact elements exposed in a ball grid array (BGA) at its external active face for mechanical and electrical connection to an external support and a semiconductor die connected electrically internally with the external contact elements. A reinforcement layer of electrically insulating material extends between and surrounds laterally peripheral contact elements of the BGA. The reinforcement layer extends to from about thirty percent (30%) to about fifty percent (50%) of the height of the peripheral contact elements at the active face.

Claims (32)

1. A surface mount semiconductor device, comprising:

an external active face;

external contact elements exposed in an array at said external active face for mechanical and electrical connection to an external support;

a semiconductor die connected electrically internally with said external contact elements; and

a reinforcement layer of electrically insulating material extending between and surrounding laterally at least peripheral ones of said external contact elements of said array, wherein said reinforcement layer comprises openings surrounding laterally respective ones of said peripheral external contact elements, and wherein said openings are tapered with the taper closing in away from the semiconductor die to form conical cavities such that said reinforcement layer contacts intimately and supports at least said peripheral external contact elements;

wherein said reinforcement layer extends to at least thirty percent (30%) of the height of said peripheral external contact elements at said active face.

2. The semiconductor device of claim 1 , wherein said reinforcement layer extends to less than fifty percent (50%) of the height of said peripheral external contact elements at said active face.

3. The semiconductor device of claim 1 , wherein said external contact elements comprise solder elements and said openings comprise solder wetting linings contacting said respective ones of said solder elements.

4. The semiconductor device of claim 1 , wherein said semiconductor die has an active face attached to said external contact elements and said reinforcement layer of electrically insulating material.

5. The semiconductor device of claim 1 , further comprising:

a substrate having internal contact elements electrically connected internally with said semiconductor die, wherein said external contact elements connect electrically internally with said internal contact elements of said substrate and are located on said substrate at said active face of said semiconductor device.

6. The semiconductor device of claim 5 , wherein said reinforcement layer of electrically insulating material adheres to said substrate.

7. The semiconductor device of claim 5 , wherein said substrate comprises laminated layers and said reinforcement layer of electrically insulating material comprises at least one of said laminated layers at said external active face.

8. A surface mount semiconductor device, comprising:

an external active face;

a substrate having internal contact elements in an array;

external contact solder elements connected mechanically and electrically to respective ones of said internal contact elements and exposed in an array at said external active face for mechanical and electrical connection to an external support;

a semiconductor die connected electrically internally with said internal contact elements; and

a reinforcement member of electrically insulating material located at said active face and extending between at least peripheral ones of said external contact solder elements of said array, wherein said reinforcement member comprises openings that laterally surround respective ones of said peripheral external contact solder elements, wherein said openings are tapered with the taper closing in away from the semiconductor die to form conical cavities such that said reinforcement member contacts and supports said peripheral external contact solder elements;

wherein said substrate includes a solder mask layer to which said reinforcement member adheres.

9. The semiconductor device of claim 8 , wherein said openings include solder wetting linings contacting said respective ones of at least said peripheral external contact solder elements.

10. A method of assembling a surface mount semiconductor device having an external active face, the method comprising:

providing a semiconductor die;

providing a substrate having an array of internal contact elements;

attaching the semiconductor die to the substrate and electrically connecting the internal contact elements to the semiconductor die;

providing a reinforcement member of electrically insulating material having an array of openings corresponding with at least peripheral ones of the internal contact elements of the array;

assembling the reinforcement member with the substrate, wherein the reinforcement member is located at said external active face; and

providing external contact elements connected electrically internally with the internal contact elements and exposed in an array at said external active face for mechanical and electrical connection to an external support;

wherein the reinforcement member extends between at least peripheral ones of said external contact elements, wherein the openings are tapered with the taper closing in away from the semiconductor die to form conical cavities such that the reinforcement member intimately contacts and supports the peripheral external contact elements.

11. The method of claim 10 , wherein the external contact elements comprise solder balls and the openings comprise solder wetting linings contacting respective ones of at least the peripheral external contact elements.

12. The method of claim 10 , wherein the reinforcement layer extends to at least thirty percent (30%) of the height of the peripheral external contact elements at the active face.

13. The method of claim 12 , wherein the reinforcement layer extends to less than fifty percent (50%) of the height of the peripheral external contact elements at the active face.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0804 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0819 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0844 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0510 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 031248/0750 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0627 →