Synchronous multiple port memory with asynchronous ports
View Patent ↗A method of operating a multiport memory, which has first and second sets of word lines and bit lines for accessing a memory array, uses a first port and a second port for accesses during a first phase of a master clock and a third port and a fourth port during a second phase of the master clock. Each port has its own port clock, which clocks their own row and column addresses, that is no faster than the master clock. Assuming there is demand for it, four accesses occur for each cycle of the master clock. This has the effect of being able to be sure that a given access is complete within two cycles of the port clocks and can be operated at the rate of one access per cycle of the port clock.
1. A method, comprising:
providing a memory system comprising a first port a second port, a third port, a fourth port, an array of memory cells, a first set of word lines and bit lines coupled to the memory cells, a second set of word lines and bit lines coupled to the memory cells, and a system clock in which each cycle has a first phase and a second phase;
applying a first clock, a first row address, and a first column address to the first port;
applying a second clock, a second row address, and a second column address to the second port;
applying a third clock, a third row address, and third column address, to the third port;
applying a fourth clock, a fourth row address, and a fourth column address to the fourth port; and
performing accesses to the array through:
the first port responsive to the system clock entering the first phase of a first cycle of the system clock and the first clock being active using the first set of word lines and bit lines during the first phase of the first cycle;
the second port responsive to the system clock entering the first phase of the first cycle and the second clock being active using the second set of word lines and bit lines if the first row address is different from the second row address during the first phase of the first cycle;
the third port responsive to the system clock entering the first phase of the first cycle and the third clock being active using the first set of word lines and bit lines during the second phase of the first cycle; and
the fourth port responsive to the system clock entering the first phase of the first cycle and the fourth clock being active using the second set of word lines and bit lines if the third row address is different from the fourth row address during the second phase of the second cycle.
2. The method of claim 1 , wherein, when the performing the accesses is further characterized by the access performed by the first port being a write, the access performed by the second port being a read, the first row address is the same as the second row address, and the first column address is the same as the second column address, the second port provides data written by the first port to the memory array as an output of the second port through circuitry not including either the first set of word lines and bit lines or the second set of word lines and bit lines.
3. The method of claim 2 , wherein, when the performing the accesses is further characterized by the access performed by the first port being a write, the access performed by the third port being a read, the first row address is the same as the third row address, and the first column address is the same as the third column address, the third port provides data by accessing the array.
4. The method of claim 2 , wherein, when the performing the accesses is further characterized by the access performed by the first port being a write, the access performed by the fourth port being a read, the first row address is the same as the fourth row address, and the first column address is the same as the fourth column address, the fourth port provides data by accessing the array.
5. The method of claim 1 , wherein the step of providing is further characterized by the first phase being from a rising edge of the system clock to a falling edge of the system clock and the second phase being from the falling edge of the system clock to the next rising edge of the system clock.
6. The method of claim 5 , wherein the performing the accesses uses a launch controller to determine if an access is to be performed for the first, second, third and fourth ports in response to the rising edge of the first cycle of the system clock.
7. The method of claim 6 , further comprising outputting data on the first port after the rising edge that ends the second phase of the first cycle of the system clock in response to a second cycle of the first clock immediately following the cycle after the first cycle of the first clock.
8. The method of claim 1 , wherein the performing the accesses is further characterized for the case of the accesses including a read through the first port in which the first cycle of the system clock is entered during a first cycle of the first clock and a result of the read is available on the first port on the beginning of the third cycle of the first port clock after the applying of the first port clock.
9. The method of claim 1 , wherein the providing is further characterized as providing a first row decoder coupled to the first port and the third port and to the word lines of the first set of word lines and bit lines and a second row decoder coupled to the second port and the fourth port and to the word lines of the second set of word lines and bit lines.
10. The method of claim 9 , wherein the performing the accesses is further characterized by the first row decoder selecting a word line, based on the first row address, of the first set of word lines and bit lines during the first phase of the first cycle and selecting a word line, based on the third row address, of the first set of word lines and bit lines during the second phase of the first cycle.
11. A memory system, comprising:
an array of memory cells coupled to a first set of word lines and bit lines and a second set of word lines and bit lines;
column circuitry coupled to the bit lines of the first and second sets;
row decoders coupled to the word lines of the first and second sets;
a first port, responsive to a first clock and a master clock, that receives a first row address and a first column address and has a first input circuit and a first output circuit;
a second port, responsive to a second clock and the master clock, that receives a second row address and a second column address and has a second input circuit and a second output circuit;
a third port, responsive to a third clock and the master clock, that receives a third row address and a third column address and has a third input circuit and a third output circuit; and
a fourth port, responsive to a fourth clock and the master clock, that receives a fourth row address and a fourth column address and has a fourth input circuit and a fourth output circuit;
wherein:
for each cycle of the master clock there is a first phase and a second phase;
during the first phase, when the first row address is different than the second row address, the first port accesses the memory array using the first set through the row decoders and the column circuitry and the second port accesses the memory array using the second set through the row decoders and the column circuitry; and
during the second phase, when the third row address is different than the fourth address, the third port accesses the memory array using the first set through the row decoders and the column circuitry and the fourth port accesses the memory array using the second set through the row decoders and the column circuitry.
12. The memory system of claim 11 , wherein the first row address is read by the first port at a beginning of a first cycle of the first clock that immediately precedes the first phase.
13. The memory system of claim 12 , wherein, when the access is a read, data is output by the first port at a beginning of a third cycle of the first clock immediately following the first cycle of the first clock.
14. The memory system of claim 12 , wherein:
the second row address is read by the second port at a beginning of a first cycle of the second clock that immediately precedes the first phase; and
when:
the access performed by the first port is a write;
the access performed by the second port is a read;
the first row address is the same as the second row address; and
the first column address is the same as the second column address,
the second port provides data written by the first port to the memory array as an output of the second port through circuitry not including either the first set of word lines and bit lines or the second set of word lines and bit lines.
15. The memory system of claim 11 , wherein during the first phase when the first row address is the same as the second row address, the first port and the second port use a word line of the first set of word lines and bit lines that is selected by the first row address to access the memory array.
16. The memory system of claim 11 , wherein the master clock has a frequency at least as great as that of the first, second, third, and fourth clocks.
17. The memory system of claim 11 , wherein:
when:
the access performed by the third port is a write;
the access performed by the fourth port is a read;
the third row address is the same as the fourth row address; and
the third column address is the same as the fourth column address,
the fourth port provides data written by the third port to the memory array as an output of the fourth port through circuitry not including either the first set of word lines and bit lines or the second set of word lines and bit lines.
18. A method of operating a multiport asynchronous memory having a memory array accessed in response to a master clock, which has a first phase and a second phase for each cycle, through a first set of word lines and bit lines and a second set of word lines and bit lines, comprising:
using a first port to access the memory array during the first phase of the master clock through the first set of word lines and bit lines responsive to a first row address and a first column address clocked by a first clock;
using a second port to access the memory array during the first phase of the master clock through the second set of word lines and bit lines responsive to a second row address and a second column address clocked by a second clock when the second row address is different from the first row address;
using a third port to access the memory array during the second phase of the master clock through the first set of word lines and bit lines responsive to a third row address and a third column address clocked by a third clock; and
using a fourth port to access the memory array during the second phase of the master clock through the second set of word lines and bit lines responsive to a fourth row address and a fourth column address clocked by a fourth clock when the fourth row address is different from the third row address.
19. The method of claim 18 , wherein when access is a read and the first address is the same as the second address, the using the second port is further characterized by using the word lines of the first set of word lines and bit lines.
20. The method of claim 18 , wherein when the access for the first port is a write and the access for the second port is a read, the using the second port is further characterized as using circuitry other than either the first set of word lines and bit lines or the second set of word lines and bit lines.