Logic transistor and non-volatile memory cell integration
View Patent ↗A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate. A sacrificial layer is formed over the barrier layer and planarized. A first patterned masking layer is formed over the sacrificial layer and control gate in the NVM region which defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer is formed in the logic region which defines a logic gate location. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location which exposes the barrier layer.
1. A non-volatile memory (NVM) cell, comprising:
a substrate ( 16 );
a select gate over the substrate ( 16 ) having a planarized to surface;
a control gate ( 32 ) over the substrate and laterally adjacent the select gate, wherein the control gate has a planarized to surface;
a nanocrystal stack ( 20 ) between the control gate and the substrate, wherein the nanocrystal stack comprises a bottom dielectric, a plurality of nanocrystals on the bottom dielectric, and a top dielectric on and around the plurality of nanocrystals;
a high-k gate dielectric ( 34 ) between the select gate and the substrate and along a first sidewall of the select gate, between the first sidewall of the select gate and a first sidewall of the control gate, wherein:
the select gate comprises a barrier metal layer ( 35 ) which is in physical contact with the high-k gate dielectric between the select gate and the substrate and between the first sidewall of the select gate and the first sidewall of the control gate;
a first source/drain region ( 44 ) in the substrate, laterally adjacent a second sidewall of the select gate, opposite the first sidewall of the select gate;
a second source/drain region ( 46 ) in the substrate, laterally adjacent a second sidewall of the control gate, opposite the first sidewall of the control gate, wherein the select gate and the control gate are between the first and second source/drain regions; and
a logic gate over the substrate having a planarized to surface that is coplanar with the planarized top surface of the control gate and the planarized top surface of the select gate.
2. The NVM cell of claim 1 , wherein the barrier metal layer further comprises a first portion adjacent a second sidewall of the control gate opposite the first sidewall of the control gate, further comprising:
a spacer adjacent the first portion of the barrier metal layer and the second sidewall of the control gate, wherein the first portion of the barrier metal layer is between the control gate and the spacer.
3. The NVM cell of claim 1 , wherein the barrier metal layer under the select gate performs a work-function-setting purpose for the NVM cell.
4. The NVM cell of claim 1 , wherein the select gate over the barrier metal layer comprises one of a group consisting of metal, polysilicon plus metal, and polysilicon.
5. The NVM cell of claim 1 , wherein the NVM cell is a portion of a semiconductor device located in an NVM portion of the semiconductor device and the semiconductor device further includes a logic transistor located in a logic portion of the semiconductor device.
6. The semiconductor device of claim 5 , wherein the barrier metal layer further comprises a second portion that functions as a work-function-setting layer of the logic transistor.
7. The semiconductor device of claim 5 , wherein the high K dielectric further comprises a first portion between the substrate and the second portion of the barrier metal layer.
8. The semiconductor device of claim 1 wherein the logic gate comprises one of a group consisting of metal, polysilicon plus metal, and polysilicon.
9. A semiconductor device having a substrate, a high K dielectric layer, and a barrier metal layer, comprising:
an NVM cell in an NVM region of the semiconductor device, the NVM cell comprising:
a select gate having a first side, a second side, and a planarized top surface, wherein the select gate is over the substrate and a first portion of the barrier metal layer is a bottom portion of the select gate;
a control gate having a first side, a second side, and a planarized to surface, wherein the first side of the control gate is adjacent the first side of the select gate and the control gate is over the substrate;
a first source/drain region in the substrate substantially aligned to the second side of the select gate;
a second source/drain region in the substrate substantially aligned to the second side of the control gate;
a charge storage layer comprising nanocrystals between the substrate and the control gate; and
a first portion of the high K dielectric layer located between the substrate and a bottom portion of the select gate; and
a logic transistor in a logic region of the semiconductor device, the logic transistor comprising:
a logic gate having a bottom portion comprising a second portion of the metal barrier layer and a planarized to surface that is coplanar with the to surface of the select gate and the top surface of the control gate;
a third source/drain region in the substrate substantially aligned to the a first side of the logic gate;
a fourth source/drain region in the substrate substantially aligned to a second side of the logic gate; and
a second portion of the high K dielectric layer located between the substrate and the bottom portion of the logic gate.
10. The semiconductor device of claim 9 , wherein the barrier metal layer performs a work-function-setting purpose.
11. The semiconductor device of claim 10 , wherein work-function-setting purpose is for the logic transistor and the NVM cell.
12. The semiconductor device of claim 9 , wherein a third portion of the high K dielectric is between the first sides of the select gate and control gate.
13. The semiconductor device of claim 12 , wherein a fourth portion of the high K dielectric is along the second side of the control gate.
14. The semiconductor device of claim 9 wherein a third portion of the metal barrier layer is along the first side of the select gate.
15. The semiconductor device of claim 9 , wherein a sidewall spacer surrounds the control gate and select gate.
16. The semiconductor device of claim 9 , wherein upper portions of the select gate and logic gate comprise one of a group consisting of metal, polysilicon plus metal, and polysilicon.