Granted Patent B2

US 9,006,093 · App. 13/928,666 · Granted Apr 14, 2015

Abstract

Claims (43)

1. A method of making a semiconductor structure comprising:

forming a select gate stack on a substrate, the substrate including a non-volatile memory (NVM) region and a high voltage region, the select gate stack being formed in the NVM region;

forming a charge storage layer over the NVM region and the high voltage region of the substrate, the charge storage layer including charge storage material; and

oxidizing the charge storage material in the high voltage region while the charge storage material in the NVM region remains unoxidized.

2. The method of claim 1 further comprising:

depositing a protective layer over the NVM region before oxidizing the charge storage material.

3. The method of claim 1 further comprising:

depositing a layer of conductive gate material over the NVM region and the high voltage region; and

depositing a protective layer over the conductive gate material in the NVM region before oxidizing the charge storage material through the conductive gate material in the high voltage region.

4. The method of claim 1 wherein the charge storage material includes one of a group consisting of: discrete charge storage elements and a layer of conductive film.

5. The method of claim 1 , wherein the substrate further includes a logic region, the method further comprising:

depositing a material used for a portion of the select gate stack in the NVM region and the logic region;

forming a memory cell including the select gate stack in the NVM region;

forming a high voltage transistor in the high voltage region; and

forming a logic transistor in the logic region after forming the memory cell and the high voltage transistor and after removing the material used for the select gate stack in the logic region.

6. The method of claim 1 wherein the charge storage layer with the oxidized charge storage material is used as a gate dielectric for a high voltage transistor in the high voltage region.

7. The method of claim 1 where the oxidizing the charge storage material comprises:

implanting oxygen in the charge storage layer in the high voltage region; and

exposing the charge storage layer to heat.

8. The method of claim 5 wherein the memory cell is a split gate memory cell.

9. The method of claim 5 , wherein:

the memory cell is configured to operate at voltages between 0 and 18 Volts;

the high voltage transistor is configured to operate at voltages between 0 and 18 Volts; and

the logic transistor is configured to operate at voltage between 0 and 3 Volts.

10. The method of claim 3 further comprising:

forming a control gate for a memory cell from the layer of conductive gate material in the NVM region; and

forming a control gate for a high voltage device cell from the layer of conductive gate material in the high voltage region.

11. A method of making a semiconductor structure comprising:

growing a select gate dielectric over a major surface of a substrate;

depositing a select gate material over the select gate dielectric;

patterning a select gate stack in a non-volatile memory (NVM) region of the substrate while removing the select gate dielectric and the select gate material in a high voltage region of the substrate and retaining the select gate dielectric and the select gate material in a logic region of the substrate;

depositing a charge storage layer over the NVM region, the high voltage region, and the logic region;

forming a protective layer over the charge storage layer in the NVM region; and

oxidizing the charge storage layer in the high voltage region and the logic region while the protective layer prevents the charge storage layer from oxidizing in the NVM region.

12. The method of claim 11 further comprising:

depositing a control gate material over the charge storage layer before the forming the protective layer and the oxidizing the charge storage layer.

13. The method of claim 11 further comprising:

patterning the control gate material and the charge storage layer in the NVM region to form a control gate partially overlapping the select gate stack.

14. The method of claim 13 further comprising:

patterning the control gate material and the oxidized charge storage layer in the high voltage region to form a gate for a high voltage device.

15. The method of claim 14 further comprising:

removing the select gate dielectric and the select gate material in the logic region of the substrate; and

forming a gate stack in the logic region after the removing the select gate dielectric and the select gate material in the logic region.

Assignments (20)