IP Library Granted Patent US 9,261,556
Granted Patent B2
US 9,261,556 · App. 13/913,993 · Granted Feb 16, 2016

Optical wafer and die probe testing

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Quick Facts
Patent No.
US 9,261,556
App. No.
13/913,993
Granted
Feb 16, 2016
Kind
B2
Abstract

An optical die probe wafer testing circuit arrangement and associated testing methodology are described for mounting a production test die ( 157 ) and surrounding scribe grid ( 156 ) to a test head ( 155 ) which is positioned over a wafer ( 160 ) in alignment with a die under test ( 163 ) and surrounding scribe grid ( 161, 165 ), such that one or more optical deflection mirrors ( 152, 154 ) in the test head scribe grid ( 156 ) are aligned with one or more optical deflection mirrors ( 162, 164 ) in the scribe grid ( 161, 165 ) for the die under test ( 163 ) to enable optical die probe testing on the die under test ( 163 ) by directing a first optical test signal ( 158 ) from the production test die ( 157 ), through the first and second optical deflection mirrors (e.g., 152, 162 ) and to the first die.

Claims (42)

1. A method comprising:

providing a wafer comprising a first die of a predetermined size surrounded by a first scribe grid comprising a first optical deflection mirror positioned in the first scribe grid for receiving an optical test signal in a first plane that is perpendicular to the lateral plane of the wafer and for perpendicularly deflecting the received optical test signal to an optical waveguide beam located in the first die;

providing a test head comprising a production test die surrounded by a second scribe grid comprising a second optical deflection mirror positioned in the second scribe grid for receiving an optical test signal in a lateral plane of the production test die and for perpendicularly deflecting the received optical test signal to a second plane that is perpendicular to the lateral plane of the production test die;

positioning the test head over the wafer to perform optical die probe testing on the first die by aligning the first optical deflection mirror and the second optical deflection mirror; and

performing optical die probe testing on the first die by directing a first optical test signal from the production test die, through the second and first optical deflection mirrors, and to the first die.

2. The method of claim 1 , where providing the wafer comprises fabricating a plurality of die formed in regular pattern on the wafer and a corresponding scribe grid surrounding each die,

where each die has a predetermined size and comprises a copy of an electro-optical circuit with a first optical waveguide beam located in a lateral plane of the wafer at a peripheral die edge of said die, and

where each scribe grid surrounding a die comprises a scribe grid optical deflection mirror which is positioned for receiving an optical test signal in a plane that is perpendicular to the lateral plane of the wafer and for perpendicularly deflecting the received optical test signal for optical communication with the first optical waveguide beam.

3. The method of claim 2 , where the production test die comprises a copy of the electro-optical circuit in each die and a second optical waveguide beam located in a lateral plane of the production test die at a peripheral die edge of the production test die, and

where the second scribe grid comprises a second scribe grid optical deflection mirror which is positioned to perpendicularly deflect an optical signal received from the second optical waveguide beam to a plane that is perpendicular to the lateral plane of the production test die.

4. The method of claim 1 , where providing the test head comprises:

packaging the production test die and surrounding second scribe grid in a packaged test die; and

attaching the packaged test die to a contact pad face on the test head comprising contact pads arranged to match a plurality of I/O pads located on the production test die.

5. The method of claim 1 , where providing the test head comprises:

attaching the production test die and surrounding second scribe grid to a contact pad face on the test head comprising contact pads arranged to match a plurality of I/O pads located on the production test die.

6. The method of claim 1 , where performing optical die probe testing on the first die comprises directing a first optical test response signal from the first die to deflect off the first optical deflection mirror and second optical deflection mirror for reception at an optical waveguide beam located in the production test die in the lateral plane of the production test die.

7. The method of claim 1 , where the first optical deflection mirror positioned in the first scribe grid comprises an angled interface deflection surface that is offset by 45 degrees from the lateral plane of the wafer.

8. The method of claim 1 , where the second optical deflection mirror positioned in the second scribe grid comprises an angled interface deflection surface that is offset by 45 degrees from the lateral plane of the production test die.

9. The method of claim 1 , where the optical waveguide beam located in the first die comprises a cantilevered silicon beam surrounded by one or more deflection electrodes, where the cantilevered silicon beam extends into a first deflection cavity which extends to the peripheral die edge of the first die and which is at least partially filled with a stabilization structure.

10. The method of claim 1 , where performing optical die probe testing on the first die comprises:

forming a recess opening in the first scribe grid of the wafer to substantially reveal at least a distal end of the first cantilevered silicon beam; and

performing optical die probe testing on the first die using at least a first optical signal that is received at the first optical deflection mirror in the first plane that is perpendicular to a lateral plane of the wafer and perpendicularly deflected at the first optical deflection mirror into the lateral plane of the wafer for transmission across the recess opening for reception at the cantilevered silicon beam.

11. The method of claim 1 , further comprising:

singulating the first die from the wafer after performing optical die probe testing; and

packaging the first die in a packaging structure.

12. A method for making an integrated circuit device comprising:

providing a wafer with a first die that is subjected to one or more optical wafer die probe tests while in wafer form; and

singulating the first die from the wafer;

where the wafer comprises a first optical waveguide beam located at a peripheral die edge of the first die, and a first scribe grid comprising a first optical deflection mirror located proximate to the peripheral die edge of the first die for perpendicularly deflecting optical signals to and/or from the first optical waveguide beam, and

where the one or more optical wafer die probe tests are performed by generating an optical test signal with a second die comprising a second optical waveguide beam located at a peripheral die edge of the second die, and a second scribe grid comprising a second optical deflection mirror located proximate to the peripheral die edge of the second die for perpendicularly deflecting optical signals to and/or from the second optical waveguide beam.

13. The method of claim 12 , where the one or more optical wafer die probe tests are performed with the second die and second scribe grid attached to a test head device.

14. The method of claim 12 , where the one or more optical wafer die probe tests are performed by:

positioning the test head device over the wafer to align the second optical deflection mirror over the first optical deflection mirror; and

performing optical die probe testing on the first die by directing a first optical test signal from the second die for perpendicular deflection off the second optical deflection mirror and first optical deflection mirror for reception at the first optical waveguide beam in the lateral plane of the first die.

15. The method of claim 14 , further comprising directing a first optical test response signal from the first die for perpendicular deflection off the first optical deflection mirror and second optical deflection mirror for reception at the second optical waveguide beam in the lateral plane of the second die.

16. The method of claim 13 , where, during testing, the second die and second scribe grid are attached to a contact pad face on the test head device comprising contact pads located on a contact pad face and arranged to match a plurality of I/O pads located on the second die.

17. The method of claim 12 , where the first optical deflection mirror comprises an angled interface deflection surface that is offset by 45 degrees from the lateral plane of the wafer.

18. An optical wafer test system comprising:

a wafer chuck for supporting a semiconductor wafer having a plurality of semiconductor die formed thereon, wherein each semiconductor die comprises a copy of an electro-optical circuit having an optical beam waveguide and is surrounded by a scribe grid comprising one or more first optical deflection mirrors having an angled deflection surface that is offset by 45 degrees from a lateral plane of the wafer and positioned for optical communication with a corresponding optical beam waveguide in the surrounded semiconductor die;

a test head device disposed over the wafer chuck for relative movement in relation to individual semiconductor die in the semiconductor wafer, the test head for holding

a packaged production test die and surrounding second scribe grid attached to the test head device, where the production test die comprises an electro-optical circuit, where the surrounding second scribe grid comprises one or more second optical deflection mirrors having an angled deflection surface that is offset by 45 degrees from a lateral plane of the production test die and positioned for optical communication with a corresponding optical beam waveguide in the surrounded production test die, and where the one or more second optical deflection mirrors are positioned for alignment with the one or more first optical deflection mirrors when the production test die is disposed over a semiconductor die under test when performing optical die probe testing on semiconductor die under test.

19. The optical wafer test system of claim 18 , where the test head device provides power and control signals to the production test die for generating optical test signals that are directed through the one or more second optical deflection mirrors in the second scribe grid for perpendicular deflection to the semiconductor die under test.

Assignments (29)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 6, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0819 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0804 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0844 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2013
From: MCSHANE, MICHAEL B.; PELLEY, PERRY H.; STEPHENS, TAB A.
To: FREESCALE SEMICONDUCTOR, INC.
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