Granted Patent B2

US 9,412,709 · App. 13/898,949 · Granted Aug 9, 2016

Abstract

Claims (39)

1. A method for fabricating a semiconductor structure comprising:

forming a conductive layer on a integrated circuit (IC) wafer;

forming a first sacrificial layer over a major surface of the conductive layer;

forming a passivation layer over the first sacrificial layer;

removing a portion of the passivation layer and a portion of the first sacrificial layer from a bond area on the major surface of the conductive layer; and

forming an encapsulating material over the passivation layer and in contact with an exposed portion of the sacrificial layer.

2. The method of claim 1 further comprising forming a conductive bond on the bond area before the forming the encapsulating material.

3. The method of claim 1 , wherein prior to the forming the passivation layer, the method further comprises:

patterning the conductive layer and the first sacrificial layer;

forming a second sacrificial layer over the patterned conductive layer and the patterned first sacrificial layer; and

etching the second sacrificial layer to form a spacer along sidewalls of the first sacrificial layer and the conductive layer.

4. The method of claim 3 wherein the removing the portion of the passivation layer and the portion of the first sacrificial layer includes removing a portion of the first sacrificial layer over the bond area to form a sacrificial anode of the first sacrificial layer while leaving the spacer intact.

5. The method of claim 3 wherein the forming the encapsulating material includes forming the encapsulating material over the passivation layer and in contact with an exposed portion of the first sacrificial layer.

6. The method of claim 2 wherein the conductive pad layer is formed of aluminum and the conductive bond is formed of copper.

7. The method of claim 1 wherein the sacrificial layer has a higher redox potential than the conductive layer.

8. The method of claim 1 wherein the forming the passivation layer comprises:

forming a first passivation layer over the major surface of the conductive layer and along the sidewalls of the conductive layer;

forming a second passivation layer over the first passivation layer;

forming a layer of photoresist to mask the first and second passivation layers round the conductive layer;

removing unmasked portions of the first and second passivation layers including forming an undercut area in the first passivation layer adjacent the major surface of the conductive layer.

9. The method of claim 8 wherein the forming the sacrificial layer comprises:

depositing the sacrificial layer over the second passivation layer, in the undercut areas and over the major surface of the conductive layer;

etching the sacrificial layer to form a sacrificial anode around the bond area.

10. A method of making a packaged semiconductor device comprising:

forming a conductive pad on an external surface of an integrated circuit device;

forming a passivation layer over the conductive pad;

removing a portion of the passivation layer over a bond area on the conductive pad;

forming a sacrificial anode around a majority of a periphery surrounding the bond area;

forming a conductive bond in the bond area; and

forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

11. The method of claim 10 wherein the forming the passivation layer includes forming a first passivation layer and a second passivation layer adjacent the periphery surrounding the bond area;

forming an undercut area in the first passivation layer so that a portion of the second passivation layer overlies the undercut area;

forming the sacrificial anode in the undercut area.

12. The method of claim 10 wherein the forming the sacrificial anode includes:

forming a first portion of the sacrificial anode around sidewalls of the conductive pad and forming a second portion of the sacrificial anode on a top surface of the conductive pad and in direct contact with the first portion of the sacrificial anode.

13. The method of claim 10 wherein the forming the sacrificial anode includes forming material with a higher redox potential than the conductive pad around sidewalls of the conductive pad.

14. The method of claim 10 wherein the conductive bond is one of a group consisting of: a wire bond, a solder bump in a ball grid array, a copper bump, a copper pillar.

15. The method of claim 10 wherein:

the sacrificial anode a higher redox potential than the conductive pad.

Assignments (11)