Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
View Patent ↗A method for fabricating a stacked microelectronic device includes attaching a first package layer to a second package layer to form stacked microelectronic layers. Saw streets of the first package layer overlie and are aligned with saw streets of the second package layer. The first and second package layers include respective edge connectors formed between the saw streets and electronic components in the first and second package layers. A through package via is formed in one of the saw streets of the first and second package layers. The via is filled with conductive material. The stacked package layers are singulated along the saw streets in a manner that retains a portion of the conductive material to form a sidewall connector between at least two of the edge connectors.
1. A method for fabricating a stacked microelectronic device, comprising:
attaching a first package layer to a second package layer to form stacked microelectronic layers, wherein saw streets of the first package layer overlie and are aligned with saw streets of the second package layer, the first and second package layers include respective edge connectors formed between the saw streets and electronic components in the first and second package layers;
forming a through package via in one of the saw streets of the stacked microelectronic layers;
filling the via with conductive material;
singulating the stacked microelectronic layers along the saw streets in a manner that retains a portion of the conductive material to form a sidewall connector between at least two of the edge connectors.
2. A method according to claim 1 wherein the plurality of sidewall conductors are formed to electrically couple the electronic devices.
3. A method according to claim 1 further comprising:
fabricating the first and second package layers including a first electronic component located in the first package layer and a second electronic component located in the second package layer, wherein the sidewall conductor electrically couples the first electric component to the second electronic component.
4. A method according to claim 1 wherein the via is wider than the saw street.
5. A method according to claim 1 further comprising cleaning the via before filling the via with the conductive material.
6. A method according to claim 1 wherein the via is circular.
7. A method according to claim 1 wherein the conductive material does not extend beyond any of the sidewalls of the stacked microelectronic device.
8. A method according to claim 1 wherein the conductive material comprises one of a group consisting of: an electrically conductive adhesive, conductive polymer, a polymer filled with conductive particles, a metal alloy, metal coated organic particles, metal coated ceramic particles, solder paste, solder-filled adhesive, nanoparticle-filled ink, a metal-containing adhesive, a metal-containing epoxy, electrically-conductive pastes, indium, and bismuth.
9. A method according to claim 1 wherein the via is rectangular.
10. A method according to claim 1 wherein the via is diamond shaped.
11. A method of fabricating stacked microelectronic devices, comprising:
stacking and bonding a plurality of package layers to one another, wherein scribe streets of the package layers overlie scribe streets of the other package layers, wherein each layer includes two or more integrated circuits separated by the scribe streets and a plurality of edge conductors having a first end coupled to a respective one of the integrated circuits and a second end extending to a respective one of the scribe streets;
forming a plurality of openings in the scribe streets after the stacking and bonding the plurality of package layers to one another, wherein each of the openings intersect at least one of the edge conductors;
filling the openings with conductive material, wherein the conductive material is in contact with at least one of the edge conductors;
cutting the stacked package layers along the scribe streets to form the stacked microelectronic devices with at least some of the conductive material remaining and being exposed on sidewalls of the stacked microelectronic devices.
12. A method according to claim 11 wherein the remaining conductive material forms a plurality of sidewall conductors.
13. A method according to claim 11 further comprising:
fabricating the package layers including mounting a first integrated circuit on a first one of the package layers and mounting a second integrated circuit on one of the second package layers, wherein the sidewall conductor electrically couples the first integrated circuit to the second integrated circuit.
14. A method according to claim 11 wherein the via is wider than the saw street.
15. A method according to claim 11 further comprising cleaning the via before filling the via with the conductive material.
16. A method according to claim 11 wherein the conductive material does not extend beyond any of the sidewalls of the stacked microelectronic devices.
17. A method according to claim 11 wherein the conductive material comprises one of a group consisting of: an electrically conductive adhesive, conductive polymer, a polymer filled with conductive particles, a metal alloy, metal coated organic particles, metal coated ceramic particles, solder paste, solder-filled adhesive, nanoparticle-filled ink, a metal-containing adhesive, a metal-containing epoxy, electrically-conductive pastes, indium, and bismuth.
18. A method according to claim 11 wherein the sidewall conductor has one of a group consisting of a semicircular cross-section, a rectangular cross-section, and a triangular cross-section.