Fuse/resistor utilizing interconnect and vias and method of making
View Patent ↗A semiconductor structure comprising a fuse/resistor structure over a functional layer having a substrate. The fuse/resistor structure includes a via, a first interconnect layer, and a second interconnect layer. The via is over the functional layer and has a first end and a second end vertically opposite the first end, wherein the first end is bounded by a first edge and a second edge opposite the first edge and the second end is bounded by a third edge and a fourth edge opposite the third edge. The first interconnect layer includes a first metal layer running horizontally and contacting the first end and completely extending from the first edge to the second edge. The second interconnect layer includes a second metal layer running horizontally and contacting the second end of the via and extending past the third edge but reaching less than half way to the fourth edge.
1. A method of making a semiconductor structure comprising forming a fuse/resistor structure over a functional layer that includes a substrate, the method of forming the fuse/resistor structure comprising:
forming a first metal layer bounded by a first insulating layer at a junction;
forming an insulating layer over the first metal layer;
forming a via having a bottom surface over the junction, wherein
said forming the via comprises forming a first opening partially through the insulating layer, forming a second opening surrounding the first opening partially through the insulating layer and extending the first opening to the junction, depositing a barrier layer in the first and second openings, and depositing a metal on the barrier layer in the first opening, and
more of the bottom surface of the via is in contact with the first insulating layer than is in contact with the first metal layer; and
forming a second metal layer over and in contact with a top area of the via.
2. The method of claim 1 , wherein the depositing a metal comprises depositing copper.
3. The method of claim 2 , wherein the depositing a barrier layer comprises depositing one of a group consisting of tantalum and titanium.
4. Blowing the fuse/resistor structure formed by the method of claim 1 by applying current through the bottom surface of the via where the bottom surface is in contact with the first metal layer.