IP Library Patent Application 13924623
Patent Application
App. No. 13/924,623

LEAD FRAME AND SEMICONDUCTOR DEVICE USING SAME

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Quick Facts
Patent No.
US None
App. No.
13/924,623
Abstract

A lead frame for a semiconductor device has a die pad for supporting a semiconductor die and intermediate lead fingers extending from a periphery of the package towards the die pad, and each having a bonding end near the die pad. Outer lead fingers are located adjacent respective tie bars edges, each outer lead finger extending from the periphery of the package towards the die pad. Each outer lead finger has a transverse region coupling two spaced longitudinal regions. The two spaced longitudinal regions each have a bonding region near the die pad. A semiconductor die is attached to the die pad and bond wires electrically couple connection pads of the semiconductor die to the bonding regions of each outer lead finger. Only one of the bond wires is bonded to the bonding region of the second longitudinal region.

Claims (37)

1 . A lead frame, comprising:

a die pad;

a frame member surrounding the die pad;

tie bars attaching the die pad to the frame member, wherein the tie bars are bent so that the die pad is downset from the frame member;

intermediate lead fingers extending from the frame member towards the die pad, the intermediate lead fingers each having a bonding end near the die pad; and

an outer lead finger adjacent a respective edge of each of the tie bars, wherein each outer lead finger extends from the frame member towards the die pad,

wherein each outer lead finger includes two spaced longitudinal regions and a transverse region coupling the two spaced longitudinal regions, and wherein the two spaced longitudinal regions each have a bonding region near the die pad.

2 . The lead frame of claim 1 , wherein each outer lead finger includes a fork with the transverse region located between the frame member and the bonding region of each of the longitudinal regions.

3 . The lead frame of claim 1 , wherein the transverse region forms part of the bonding region of each of the longitudinal regions.

4 . The lead frame of claim 1 , wherein a support tape is attached to an underside of the intermediate lead fingers and the longitudinal regions.

5 . A method of forming a semiconductor die package, the method comprising the steps of:

providing a lead frame with a frame member surrounding a die pad, the lead frame having tie bars attaching the die pad to the frame member, the tie bars having an angled section that down sets the die pad from the frame member, intermediate lead fingers extending from the frame member towards the die pad, and an outer lead finger adjacent a respective edge of each one of the tie bars, wherein each outer lead finger extends from the frame member towards the die pad, and wherein each outer lead finger includes a transverse region coupling two spaced longitudinal regions each having a bonding region near the die pad, and wherein the two spaced longitudinal regions are a first longitudinal region and second longitudinal region located between the first longitudinal region and one of the tie bars;

attaching a semiconductor die to the die pad;

selectively electrically coupling, with bond wires, connection pads of the semiconductor die to the bonding regions of each outer lead finger, wherein no more than one of the bond wires is bonded to the bonding region of the second longitudinal region;

encapsulating the semiconductor die and bonding regions with an encapsulant; and

detaching from the frame member the tie bars, the intermediate lead fingers, and each outer lead finger.

6 . The method of packaging a semiconductor die of claim 5 , further comprising bending ends of all of the intermediate lead fingers and an end of each outer lead finger to form mounting feet.

7 . The method of packaging a semiconductor die of claim 5 , wherein the selectively electrically coupling is characterized by there being more than one bond wire bonded to the bonding region of the first longitudinal region.

8 . The method of packaging a semiconductor die of claim 7 , wherein the selectively electrically coupling includes wire bonding the connection pads of the semiconductor die to bonding ends of the intermediate lead fingers.

9 . The method of packaging a semiconductor die of claim 5 , wherein each outer lead finger includes a fork with the transverse region located between the mounting feet and the bonding region of each of the longitudinal regions.

10 . The method of packaging a semiconductor die of claim 8 , wherein the transverse region forms part of the bonding region of each of the longitudinal regions.

11 . The method of packaging a semiconductor die of claim 5 , wherein a support tape is attached to an underside of the intermediate lead fingers and the longitudinal regions.

12 . The method of packaging a semiconductor die of claim 5 , wherein the providing is characterized by the lead frame being supported on a lead frame support having a recessed central die pad support region and slots, and wherein the die pad is located in and supported by the die pad support region and each angled section is located in a respective one of the slots.

13 . A semiconductor device, comprising:

a die pad;

a semiconductor die attached to the die pad;

intermediate lead fingers extending from a periphery of the package towards the die pad, the intermediate lead fingers each having a bonding end near the die pad;

an outer lead finger adjacent a respective edge of each one of a tie bar, each outer lead finger extending from the periphery of the package towards the die pad and wherein each outer lead finger includes two spaced longitudinal regions and a transverse region coupling the two spaced longitudinal regions, wherein the two spaced longitudinal regions each have a bonding region near the die pad;

first bond wires selectively electrically coupling connection pads of the semiconductor die to the bonding regions of the outer lead fingers, wherein only one of the first bond wires is bonded to the bonding region of the second longitudinal region; and

an encapsulant covering the bond wires and the semiconductor die.

14 . The semiconductor device of claim 13 , further comprising second bond wires selectively connecting the connection pads of the semiconductor die to the bonding ends of respective ones of the intermediate lead fingers.

15 . The semiconductor device of claim 14 , wherein ends of each outer lead finger are bent to form a mounting foot.

16 . The semiconductor device of claim 15 , wherein each outer lead finger includes a fork with the transverse region located between the mounting foot and the bonding region of each of the longitudinal regions.

17 . The semiconductor device of claim 14 , wherein the transverse region forms part of the bonding region of each of the longitudinal regions.

18 . The semiconductor device of claim 14 , wherein only one first bond wire is connected to the bonding region of the first longitudinal region.

19 . The semiconductor device of claim 14 , wherein the die pad is downset from the bonding region.

20 . The semiconductor device of claim 14 , wherein ends of all of the intermediate lead fingers and an end of each outer lead finger are bent to form mounting feet for the semiconductor device.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 6, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037445/0592 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0819 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0804 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0844 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0698 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 031248/0750 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0627 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0510 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2013
From: LEE, YIT MENG; AU, YIN KHENG; GUNN, QUENTIN D.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030667/0387 →