IP Library Granted Patent US 8,970,283
Granted Patent B2
US 8,970,283 · App. 13/989,288 · Granted Mar 3, 2015

Switching arrangement, integrated circuit comprising same, method of controlling a switching arrangement, and related computer program product

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,970,283
App. No.
13/989,288
Granted
Mar 3, 2015
Kind
B2
Abstract

There is disclosed a switching arrangement comprising a switch with a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail. Each of the elementary switches can be in either one of a closed state and an open state independently of the others. A controller is adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch. The number of elementary switches in the closed state is variable. The higher is the intensity of the current, the higher the number of elementary switches in the closed state. Thus, the impedance of the switch decreases when the current increases, and vice versa, and the voltage drop across the switch may be kept substantially constant.

Claims (37)

1. A switching arrangement, comprising:

a switch comprising a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail, each of said elementary switches being in either one of a closed state and an open state independently of the others; and

a controller adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch, wherein the number of elementary switches in the closed state is variable and wherein the higher is the intensity of the current the higher the number of elementary switches in the closed state, wherein the controller comprises a current-sense block adapted to generate a current-sense value representative of the intensity of the current flowing through the switch.

2. The switching arrangement of claim 1 , wherein the controller is further adapted to receive, from a load supplied by the second supply rail, a current value indication representative of the intensity of the current flowing through the switch, and to control the closing or opening of the elementary switches responsive to said current value indication.

3. The switching arrangement of claim 1 , wherein the current-sense block comprises a shunt resistor arranged in the current path between the first voltage rail and the second voltage rail, and a shunt resistor current measurement circuitry which is coupled to said shunt resistor.

4. The switching arrangement of claim 3 , wherein the shunt resistor current measurement circuitry comprises a differential amplifier having differential inputs respectively coupled to shunt resistor terminals to measure the voltage drop across the shunt resistor, and at least one output delivering the current-sense value.

5. The switching arrangement of claim 1 , wherein the controller further comprises a switch control block adapted to generate control signals controlling the state of the elementary switches responsive to a current value indication and/or the current-sense value.

6. The switching arrangement of claim 5 , wherein the switch control block is adapted to generate a current value information based on the current value indication and/or the current-sense value, and based further on at least one additional information among operation mode information and frequency of operation information.

7. The switching arrangement of claim 5 , wherein the switch control block comprises a coding table adapted to output, responsive to at least the current value indication and/or the current-sense value or responsive to the current value information a control value on N bits, where N is the number of elementary switches to be controlled, each of which corresponding to a respective one of the control signals.

8. The switching arrangement of claim 7 , wherein the coding table is further adapted to output the control value responsive, further, to at least one of additional information among information comprising:

manufacturing process information associated with the elementary switches;

operating voltage information; and

operating temperature information.

9. The switching arrangement of claim 7 , wherein the coding table is adapted to maintain the voltage drop across the switch substantially constant over an operational current intensity variation range.

10. The switching arrangement of claim 7 , wherein the switch control block comprises a microcontroller and wherein the coding table is stored in a memory of said microcontroller.

11. An integrated circuit comprising:

a first supply rail and a second supply rail;

a circuitry supplied by the second supply rail; and,

a power gating switch, arranged between the first voltage rail and the second voltage rail to shut off power supply from the first supply rail to the circuitry, the power gating switch includes a switching arrangement including:

a switch comprising a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail each of said elementary switches being in either one of a closed state and an open state independently of the others; and

a controller adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch, wherein the number of elementary switches in the closed state is variable and wherein the higher is the intensity of the current the higher the number of elementary switches in the closed state, wherein the controller comprises a current-sense block adapted to generate a current-sense value representative of the intensity of the current flowing through the switch.

12. The integrated circuit of claim 9 , wherein the first supply rail is a positive supply rail and the second supply rail is a virtual positive supply rail, and wherein each of the elementary switches comprises a PMOS transistor.

13. The integrated circuit of claim 1 , wherein the first supply rail is a ground rail and the second supply rail is a virtual ground rail, and wherein each of the elementary switches comprises a NMOS transistor.

14. A method of controlling a switching arrangement comprising:

closing an intermediate number of elementary switches among a plurality of individually controllable elementary switches of a switch, which are connected in parallel between a first supply rail and a second voltage rail, each of said elementary switches being in either one of a closed state and an open state independently of the others;

sensing the intensity of a current flowing through the switch between the first supply rail and the second supply rail;

generating a current-sense value representative of the intensity of the current flowing through the switch by measuring a voltage drop across a shunt resistor arranged in the current path between the first voltage rail and the second voltage rail;

generating control signals controlling the state of the elementary switches responsive to the current-sense value; and

dynamically controlling the closing or opening of the elementary switches, depending on the control signals, wherein the number of elementary switches in the closed state is variable and wherein the higher is the intensity of the current the higher the number of elementary switches in the closed state.

15. The method of claim 14 , further comprising:

receiving a current value indication from a load supplied by the second supply rail; and

generating control signals controlling the state of the elementary switches responsive to the current value indication.

16. The method of claim 14 , further comprising generating a current value information based on the current value indication and/or the current-sense value, and based further on at least one additional information among operation mode information and frequency of operation information, and generating the control signals controlling the state of the elementary switches responsive to said current value information.

17. The method of claim 14 , wherein generating the control signals controlling the state of the elementary switches comprises using a coding table which outputs, responsive to at least the current value indication and/or the current-sense value, or responsive to the current value information, a control value on N bits, where N is the number of elementary switches of the switch to be controlled, each of which bits corresponding to a respective one of the control signals.

18. The integrated circuit of claim 11 , wherein the current-sense block comprises a shunt resistor arranged in the current path between the first voltage rail and the second voltage rail, and a shunt resistor current measurement circuitry which is coupled to said shunt resistor.

19. The integrated circuit of claim 11 , wherein the controller further comprises a switch control block adapted to generate control signals controlling the state of the elementary switches responsive to the current value indication and/or the current-sense value.

20. The integrated circuit of claim 19 , wherein the shunt resistor current measurement circuitry comprises a differential amplifier having differential inputs respectively coupled to shunt resistor terminals to measure the voltage drop across the shunt resistor, and at least one output delivering the current-sense value.

Assignments (26)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2018
From: NXP USA, INC.
To: VLSI TECHNOLOGY LLC
Reel/Frame 045084/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0804 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0819 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0844 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 031248/0750 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0627 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0698 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0510 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2013
From: PRIEL, MICHAEL; ROZEN, ANTON; SEIDENWAR, YAAKOVS
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 030476/0661 →