Integrated circuits and methods for monitoring forward and reverse back biasing
View Patent ↗An integrated circuit includes a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; and a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the first well is outside of the first voltage range, providing a first out of range indicator.
1. An integrated circuit, comprising:
a device of a first conductivity type formed in a first well;
a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator;
a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the first well is outside of the first voltage range, providing a first out of range indicator.
2. The integrated circuit of claim 1 , further comprising:
a first resistive ladder coupled to a band gap reference voltage output by the second band gap reference generator and configured to provide each of the upper limit and lower limit to the monitor circuit.
3. The integrated circuit of claim 2 , further comprising:
a second resistive ladder coupled to a band gap reference voltage output by the first band gap reference generator and configured to provide the first reference voltage.
4. The integrated circuit of claim 1 , wherein the first out of range indicator comprises:
a first upper out of range indicator; and
a first lower out of range indicator.
5. The integrated circuit of claim 4 , wherein the monitor circuit is configured to assert the first upper out of range indicator when a voltage of the first well exceeds the upper limit and to assert the first lower out of range indicator when the voltage of the first well is below the lower limit.
6. The integrated circuit of claim 5 , wherein the monitor circuit is configured to assert the first out of range indicator when either the first upper out of range indicator or the first lower out of range indicator is asserted.
7. The integrated circuit of claim 4 , wherein the monitor circuit comprises:
a first comparator which has a first input coupled to receive the upper limit, a second input coupled to the first well, and an output which provides the first upper out of range indicator; and
a second comparator which has a first input coupled to receive the lower limit, a second input coupled to the first well, and an output which provides the first lower out of range indicator.
8. The integrated circuit of claim 7 , wherein the first conductivity type is n-type, and the first well is further characterized as a p-type well.
9. The integrated circuit of claim 8 , further comprising:
an inverting gain-stage circuit coupled between the first well and the second input of the first comparator, wherein the inverting gain-stage circuit has an input coupled to the first well and an output coupled to the second input of the first comparator.
10. The integrated circuit of claim 1 , further comprising:
a second device of a second conductivity type, opposite the first conductivity type, formed in a second well;
a second voltage regulator configured to provide a second bias voltage to the second well, based on a second reference voltage which is generated using the first band gap reference generator; and
a second monitor circuit configured to compare a voltage of the second well to an upper limit and a lower limit of a second voltage range, wherein each of the upper limit and lower limit of the second voltage range is provided using the second band gap reference generator, wherein, in response to determining that the voltage of the second well is outside of the second voltage range, providing a second out of range indicator.
11. The integrated circuit of claim 10 , further comprising:
a first resistive ladder coupled to a first band gap reference voltage output by the second band gap reference generator and configured to provide each of the upper limit and lower limit of the first voltage range to the monitor circuit;
a second resistive ladder coupled to a second band gap reference voltage output by the second band gap reference generator and configured to provide each of the upper limit and lower limit of the second voltage range to the second monitor circuit.
12. The integrated circuit of claim 11 , further comprising:
a third resistive ladder coupled to a first band gap reference voltage output by the first band gap reference generator and configured to provide the first reference voltage; and
a fourth resistive ladder coupled to a second band gap reference voltage output by the first band gap reference generator and configured to provide the second reference voltage.
13. The integrated circuit of claim 1 , further comprising:
self test circuitry configured to test the monitor circuits.
14. A method comprising:
generating a bias voltage based on a first band gap reference voltage that is generated by a first band gap reference generator;
providing the bias voltage to a first well of an integrated circuit, in which the first well comprises at least one device of a first conductivity type;
generating an upper voltage limit reference and a lower voltage limit reference based on a second band gap reference voltage that is generated by a second band gap reference generator;
determining if a voltage of the first well is within a voltage range defined by the upper and lower voltage limit references; and
in response to the determining, providing an out of range indicator.
15. The method of claim 14 , wherein the determining if the voltage of the first well is within the voltage range further comprises:
comparing the voltage at the first well with the upper voltage limit reference; and
comparing the voltage at the first well with the lower voltage limit reference.
16. The method of claim 15 , wherein providing the out of range indicator comprises:
asserting the out of range indicator if either the voltage at the first well exceeds the upper voltage limit reference or the voltage at the first well is less than the lower voltage limit reference.
17. An integrated circuit, comprising:
an n-type device formed in a p-type well;
a p-type device formed in an n-type well;
a first voltage regulator configured to provide a first bias voltage to the p-type well based on a first reference voltage which is generated using a first band gap reference generator;
a second voltage regulator configured to provide a second bias voltage to the n-type well based on a second reference voltage which is generated using the first bad gap reference generator;
a monitor circuit configured to:
compare a voltage of the p-type well to a first voltage range, wherein limits of the first voltage range are provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the p-type well is outside of the first voltage range, providing a first out of range indicator; and
compare a voltage of the n-type well to a second voltage range, wherein limits of the second voltage range are provided using the second band gap reference generator, wherein, in response to determining that the voltage of the n-type well is outside of the second voltage range, providing a second out of range indicator.
18. The integrated circuit of claim 17 , further comprising:
a first resistive ladder coupled to a first band gap reference voltage output by the second band gap reference generator and configured to provide the limits of the first voltage range to the monitor circuit;
a second resistive ladder coupled to a second band gap reference voltage output by the second band gap reference generator and configured to provide the limits of the second voltage range to the monitor circuit.
19. The integrated circuit of claim 18 , further comprising:
a third resistive ladder coupled to a first band gap reference voltage output by the first band gap reference generator and configured to provide the first reference voltage; and
a fourth resistive ladder coupled to a second band gap reference voltage output by the first band gap reference generator and configured to provide the second reference voltage.
20. The integrated circuit of claim 17 , further comprising:
self test circuitry configured to test the monitor circuit.