Semiconductor devices with different dielectric thicknesses
View Patent ↗An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
1. An integrated circuit, comprising:
a first semiconductor device having a first active region, the first active region underlying a first electrode stack, wherein the first active region comprises:
a first layer comprising at least one selected from the group consisting of germanium and carbon; and
a first cap layer overlying the first layer, the first cap layer comprising silicon and substantially no carbon or germanium, and the first cap layer having a first thickness;
a second semiconductor device having a second active region, the second active region underlying a second electrode stack, wherein the second active region comprises:
a second layer comprising at least one selected from the group consisting of germanium and carbon; and
a second cap layer overlying the second layer, the second cap layer comprising silicon and substantially no carbon or germanium, and the second cap layer having a second thickness;
a third semiconductor device having a third active region, the third active region underlying a third electrode stack, wherein the third active region comprises:
a third layer comprising at least one selected from the group consisting of germanium and carbon; and
a third cap layer overlying the third layer, the third cap layer comprising silicon and substantially no carbon or germanium, and the third cap layer having a third thickness;
wherein the first semiconductor device, the second semiconductor device, and the third semiconductor device have a same conductivity type, and wherein the first thickness and the second thickness are different;
wherein the first electrode stack comprises a first electrode dielectric, the second electrode stack comprises a second electrode dielectric, and the third electrode stack comprises a third electrode dielectric, wherein a thickness of the first electrode dielectric is less than a thickness of the second electrode dielectric and the thickness of the second electrode dielectric is less than a thickness of the third electrode dielectric.
2. The integrated circuit as in claim 1 , wherein the first semiconductor device comprises a first p-channel transistor, and wherein the second semiconductor device comprises a second p-channel transistor.
3. The integrated circuit as in claim 1 , wherein the first electrode dielectric including a first high-k dielectric layer overlying the first cap layer, the second electrode dielectric including an oxide layer overlying the second cap layer, and wherein the second electrode dielectric comprises a second high-k dielectric layer overlying the oxide layer.
4. The integrated circuit as in claim 3 , wherein the first semiconductor device comprises a first p-channel transistor, and wherein the second semiconductor device comprises a second p-channel transistor.
5. The integrated circuit as in claim 3 , wherein the first semiconductor device comprises a first n-channel transistor, and wherein the second semiconductor device comprises a second n-channel transistor.
6. The integrated circuit as in claim 3 , wherein the third electrode stack comprises a second oxide layer, the second oxide layer overlying the third cap layer, the second oxide layer is of a different thickness than the oxide layer.
7. The integrated circuit as in claim 6 , wherein the third electrode stack comprises a third high-k dielectric layer overlying the second oxide layer.
8. An integrated circuit as in claim 1 , wherein the first semiconductor device comprises a first n-channel transistor, and wherein the second semiconductor device comprises a second n-channel transistor.
9. An integrated circuit, comprising:
a first semiconductor device having a first active region, the first active region underlying a first electrode stack, wherein the first active region comprises:
a first layer comprising at least one selected from the group consisting of germanium and carbon; and
a first cap layer overlying the first layer, the first cap layer comprising silicon and substantially no carbon or germanium, and the first cap layer having a first thickness;
a second semiconductor device having a second active region, the second active region underlying a second electrode stack, wherein the second active region comprises:
a second layer comprising at least one selected from the group consisting of germanium and carbon; and
a second cap layer overlying the second layer, the second cap layer comprising silicon and substantially no carbon or germanium, and the second cap layer having a second thickness;
wherein the first semiconductor device and the second semiconductor device have a same conductivity type, and wherein the first thickness and the second thickness are different;
wherein the first electrode stack comprises a first electrode dielectric, the first electrode dielectric including a first high-k dielectric layer overlying the first cap layer, wherein the second electrode stack comprises a second electrode dielectric, the second electrode dielectric including an oxide layer overlying the second cap layer, and wherein the second electrode dielectric comprises a second high-k dielectric layer overlying the oxide layer;
a third semiconductor device having a third active region, the third active region underlying a third electrode stack, wherein the third active region comprises:
a third layer comprising at least one selected from the group consisting of germanium and carbon; and
a third cap layer overlying the third layer, the third cap layer comprising silicon and substantially no carbon or germanium, and the third cap layer having a third thickness,
wherein the third electrode stack comprises a third high-k dielectric layer and a second oxide layer, the third high-k dielectric layer and the second oxide layer overlying the third cap layer, the second oxide layer is of a different thickness than the oxide layer;
wherein a thickness of the first electrode dielectric is less than a thickness of the second electrode dielectric.
10. The integrated circuit as in claim 9 , wherein the first semiconductor device comprises a first p-channel transistor, and wherein the second semiconductor device comprises a second p-channel transistor.
11. The integrated circuit as in claim 10 , wherein the third semiconductor device comprises a third p-channel transistor.
12. The integrated circuit as in claim 9 , wherein the first semiconductor device comprises a first n-channel transistor, and wherein the second semiconductor device comprises a second n-channel transistor.
13. The integrated circuit as in claim 12 , wherein the third semiconductor device comprises a third n-channel transistor.
14. The integrated circuit as in claim 9 , wherein the third electrode stack comprises a third electrode dielectric, the thickness of the second electrode dielectric is less than a thickness of the third electrode dielectric.
15. An integrated circuit, comprising:
a first semiconductor device having a first active region, the first active region underlying a first electrode stack, wherein the first active region comprises:
a first layer comprising at least one selected from the group consisting of germanium and carbon; and
a first cap layer overlying the first layer, the first cap layer comprising silicon and substantially no carbon or germanium, and the first cap layer having a first thickness;
a second semiconductor device having a second active region, the second active region underlying a second electrode stack, wherein the second active region comprises:
a second layer comprising at least one selected from of the group consisting of germanium and carbon; and
a second cap layer overlying the second layer, the second cap layer comprising silicon and substantially no carbon or germanium, and the second cap layer having a second thickness;
wherein the first semiconductor device and the second semiconductor device have a same conductivity type, and wherein the first thickness and the second thickness are different;
wherein the first electrode stack comprises a first electrode dielectric, the first electrode dielectric including a first high-k dielectric layer overlying the first cap layer, wherein the second electrode stack comprises a second electrode dielectric, the second electrode dielectric including an oxide layer overlying the second cap layer, and wherein the second electrode dielectric comprises a second high-k dielectric layer overlying the oxide layer;
a third semiconductor device having a third active region, the third active region underlying a third electrode stack, wherein the third active region comprises:
a third layer comprising at least one selected from the group consisting of germanium and carbon; and
a third cap layer overlying the third layer, the third cap layer comprising silicon and substantially no carbon or germanium, and the third cap layer having a third thickness,
wherein the third electrode stack comprises a third high-k dielectric layer and a second oxide layer, the third high-k dielectric layer and a second oxide layer overlying the third cap layer, the second oxide layer is of a different thickness than the oxide layer.
16. The integrated circuit as in claim 15 , wherein the first semiconductor device comprises a first p-channel transistor, and wherein the second semiconductor device comprises a second p-channel transistor.
17. The integrated circuit as in claim 16 , wherein the third semiconductor device comprises a third p-channel transistor.
18. The integrated circuit as in claim 15 , wherein the first semiconductor device comprises a first n-channel transistor, and wherein the second semiconductor device comprises a second n-channel transistor.
19. The integrated circuit as in claim 18 , wherein the third semiconductor device comprises a third n-channel transistor.