IP Library Granted Patent US 9,810,843
Granted Patent B2
US 9,810,843 · App. 13/914,178 · Granted Nov 7, 2017

Optical backplane mirror

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Quick Facts
Patent No.
US 9,810,843
App. No.
13/914,178
Granted
Nov 7, 2017
Kind
B2
Abstract

An integrated circuit optical backplane die and associated semiconductor fabrication process are described for forming optical backplane mirror structures for perpendicularly deflecting optical signals out of the plane of the optical backplane die by selectively etching an optical waveguide semiconductor layer ( 103 ) on an optical backplane die wafer using an orientation-dependent anisotropic wet etch process to form a first recess opening ( 107 ) with angled semiconductor sidewall surfaces ( 106 ) on the optical waveguide semiconductor layer, where the angled semiconductor sidewall surfaces ( 106 ) are processed to form an optical backplane mirror ( 116 ) for perpendicularly deflecting optical signals to and from a lateral plane of the optical waveguide semiconductor layer.

Claims (59)

1. A semiconductor fabrication process comprising:

providing a wafer comprising an optical waveguide semiconductor structure;

selectively etching the optical waveguide semiconductor structure with an anisotropic wet etch process to form an angled semiconductor sidewall surface on the optical waveguide semiconductor structure; and

processing the angled semiconductor sidewall surface on the optical waveguide semiconductor structure to form a mirror for deflecting optical signals into and out of a lateral plane that is parallel to a major wafer substrate surface,

where the wafer comprises a semiconductor-on-insulator (SOI) substrate with an optical through-semiconductor via structure formed in the SOI substrate in optical alignment with the mirror.

2. The process of claim 1 , where providing the wafer comprises providing a semiconductor-on-insulator substrate comprising an optical waveguide silicon layer formed over a buried oxide layer.

3. The process of claim 1 , where the optical waveguide semiconductor structure comprises a silicon layer located over a buried oxide layer.

4. The process of claim 1 , where the anisotropic wet etch process comprises an etchant having high crystallographic plane selectivity, said etchant including at least one of the group consisting of KOH, EDP, TMAH, N 2 H 4 , and CsOH.

5. The process of claim 1 , where the anisotropic wet etch process comprises a silicon orientation-dependent wet etch process that produces a first recess opening with 45 degree angled semiconductor sidewall surfaces.

6. The process of claim 1 , where processing the angled semiconductor sidewall surface comprises:

selectively forming one or more patterned oxidation protection layers on the angled semiconductor sidewall surface of the optical waveguide semiconductor structure to expose a first portion of the optical waveguide semiconductor structure defining a first angled semiconductor sidewall surface and to cover a second portion of the optical waveguide semiconductor structure;

oxidizing the first portion of the optical waveguide semiconductor structure with a semiconductor oxidation process to produce an oxide layer with an angled oxide sidewall surface substantially parallel to where the first angled semiconductor sidewall surface was located prior to oxidation;

removing at least the one or more patterned oxidation protection layers to form a recess opening in the wafer; and

growing an epitaxial semiconductor layer in the recess opening from at least the second portion of the optical waveguide semiconductor structure to form the mirror at an interface between the epitaxial semiconductor layer and the angled oxide sidewall surface.

7. The process of claim 6 , where oxidizing the first portion of the optical waveguide semiconductor structure comprises performing a LOCal Oxidation of Silicon (LOCOS) process to thermally oxidize the first portion of the optical waveguide semiconductor structure.

8. The process of claim 1 , where processing the angled semiconductor sidewall surface comprises:

selectively forming one or more patterned oxidation protection layers to cover a first angled semiconductor sidewall surface of the optical waveguide semiconductor structure and to expose a second angled semiconductor sidewall surface of the optical waveguide semiconductor structure;

oxidizing the second angled semiconductor sidewall surface with a semiconductor oxidation process to produce an oxide mirror layer substantially parallel to the second angled semiconductor sidewall surface was located prior to oxidation;

removing at least the one or more patterned oxidation protection layers to form a recess opening in the wafer which exposes the first angled semiconductor sidewall surface; and

growing an epitaxial semiconductor layer in the recess opening from at least the first angled semiconductor sidewall surface of the optical waveguide semiconductor structure to form the mirror at an interface between the epitaxial semiconductor layer and the oxide mirror layer.

9. The process of claim 1 , where processing the angled semiconductor sidewall surface comprises:

selectively forming one or more patterned dielectric mirror layers to directly cover a first angled semiconductor sidewall surface of the optical waveguide semiconductor structure which is aligned with the optical through-semiconductor via formed in the substrate, and to expose a second angled semiconductor sidewall surface of the optical waveguide semiconductor structure; and

forming a planarized optical semiconductor layer over the one or more patterned dielectric mirror layers on the first angled semiconductor sidewall surface by growing an epitaxial semiconductor layer from at least the exposed second angled semiconductor sidewall surface of the optical waveguide semiconductor structure.

10. The process of claim 1 , where processing the angled semiconductor sidewall surface comprises forming a mirror for perpendicularly deflecting optical signals into and out of the lateral plane.

11. The process of claim 1 , where the mirror is positioned to deflect optical signals between the optical waveguide semiconductor structure in the lateral plane and the optical through-semiconductor via structure below.

12. The process of claim 1 , where the mirror comprises a half mirror.

13. The process of claim 1 , where the mirror comprises a full mirror.

14. A semiconductor fabrication process comprising:

providing a wafer comprising an optical waveguide semiconductor structure;

selectively etching the optical waveguide semiconductor structure with an anisotropic silicon orientation-dependent wet etch process to form an angled semiconductor sidewall surface on the optical waveguide semiconductor structure by etching a first recess opening with 45 degree angled semiconductor sidewall surfaces; and

processing the angled semiconductor sidewall surface on the optical waveguide semiconductor structure to form a mirror for deflecting optical signals into and out of a lateral plane that is parallel to a major wafer substrate surface,

where the wafer comprises a semiconductor-on-insulator (SOI) substrate with an optical through-semiconductor via structure formed in the SOI substrate in optical alignment with the mirror.

15. The process of claim 14 , where providing the wafer comprises providing a semiconductor-on-insulator substrate comprising an optical waveguide silicon layer formed over a buried oxide layer.

16. The process of claim 14 , where the optical waveguide semiconductor structure comprises a silicon layer located over a buried oxide layer.

17. The process of claim 14 , where the anisotropic wet etch process comprises an etchant having high crystallographic plane selectivity, said etchant including at least one of the group consisting of KOH, EDP, TMAH, N2H4, and CsOH.

18. A semiconductor fabrication process comprising:

providing a wafer comprising an optical waveguide semiconductor structure;

selectively etching the optical waveguide semiconductor structure with an anisotropic wet etch process to form an angled semiconductor sidewall surface on the optical waveguide semiconductor structure;

selectively forming one or more patterned oxidation protection layers on the angled semiconductor sidewall surface of the optical waveguide semiconductor structure to expose a first portion of the optical waveguide semiconductor structure defining a first angled semiconductor sidewall surface and to cover a second portion of the optical waveguide semiconductor structure;

oxidizing the first portion of the optical waveguide semiconductor structure with a semiconductor oxidation process to produce an oxide layer with an angled oxide sidewall surface substantially parallel to where the first angled semiconductor sidewall surface was located prior to oxidation;

removing at least the one or more patterned oxidation protection layers to form a recess opening in the wafer; and

growing an epitaxial semiconductor layer in the recess opening from at least the second portion of the optical waveguide semiconductor structure to form a mirror at an interface between the epitaxial semiconductor layer and the angled oxide sidewall surface for deflecting optical signals into and out of a lateral plane that is parallel to a major wafer substrate surface;

where the wafer comprises a semiconductor-on-insulator (SOI) substrate with an optical through-semiconductor via structure formed in the SOI substrate in optical alignment with the mirror.

19. The process of claim 18 , where oxidizing the first portion of the optical waveguide semiconductor structure comprises performing a LOCal Oxidation of Silicon (LOCOS) process to thermally oxidize the first portion of the optical waveguide semiconductor structure.

20. A semiconductor fabrication process comprising:

providing a wafer comprising an optical waveguide semiconductor structure;

selectively etching the optical waveguide semiconductor structure with an anisotropic wet etch process to form an angled semiconductor sidewall surface on the optical waveguide semiconductor structure;

selectively forming one or more patterned oxidation protection layers to cover a first angled semiconductor sidewall surface of the optical waveguide semiconductor structure and to expose a second angled semiconductor sidewall surface of the optical waveguide semiconductor structure;

oxidizing the second angled semiconductor sidewall surface with a semiconductor oxidation process to produce an oxide mirror layer substantially parallel to the second angled semiconductor sidewall surface was located prior to oxidation;

removing at least the one or more patterned oxidation protection layers to form a recess opening in the wafer which exposes the first angled semiconductor sidewall surface; and

growing an epitaxial semiconductor layer in the recess opening from at least the first angled semiconductor sidewall surface of the optical waveguide semiconductor structure to form a mirror at an interface between the epitaxial semiconductor layer and the oxide mirror layer for deflecting optical signals into and out of a lateral plane that is parallel to a major wafer substrate surface;

where the wafer comprises a semiconductor-on-insulator (SOI) substrate with an optical through-semiconductor via structure formed in the SOI substrate in optical alignment with the mirror.

21. A semiconductor fabrication process comprising:

providing a wafer comprising an optical waveguide semiconductor structure;

selectively etching the optical waveguide semiconductor structure with an anisotropic wet etch process to form an angled semiconductor sidewall surface on the optical waveguide semiconductor structure; and

processing the angled semiconductor sidewall surface on the optical waveguide semiconductor structure to form a mirror for deflecting optical signals into and out of a lateral plane that is parallel to a major wafer substrate surface by:

selectively forming one or more patterned dielectric mirror layers to directly cover a first angled semiconductor sidewall surface of the optical waveguide semiconductor structure which is aligned with the optical through-semiconductor via formed in the substrate, and to expose a second angled semiconductor sidewall surface of the optical waveguide semiconductor structure; and

forming a planarized optical semiconductor layer over the one or more patterned dielectric mirror layers on the first angled semiconductor sidewall surface by growing an epitaxial semiconductor layer from at least the exposed second angled semiconductor sidewall surface of the optical waveguide semiconductor structure;

where the wafer comprises a semiconductor-on-insulator (SOI) substrate with an optical through-semiconductor via structure formed in the SOI substrate in optical alignment with the mirror.

Assignments (24)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 6, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037445/0592 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0804 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0819 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0844 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 031248/0750 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031248/0510 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Sep 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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