Nonvolatile latch circuit and logic circuit, and semiconductor device using the same
To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.
1. A latch circuit comprising:
a latch portion; and
a data holding portion for holding data of the latch portion,
the latch portion comprising:
a first element; and
a second element,
wherein an output of the first element is electrically connected to an input of the second element, and an output of the second element is electrically connected to an input of the first element, and
wherein the input of the first element is electrically connected to a first wiring configured to be supplied with an input signal, and the output of the first element is electrically connected to a second wiring configured to be supplied with an output signal,
the data holding portion comprising:
a transistor;
a capacitor; and
an inverter,
wherein a channel formation region of the transistor includes an oxide semiconductor layer,
wherein an input of the inverter is electrically connected to the capacitor,
wherein the inverter includes an n-channel transistor and a p-channel transistor, and
wherein the oxide semiconductor layer contains indium, gallium, and zinc.
2. The latch circuit according to claim 1 ,
wherein one of a source and a drain of the transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the transistor is electrically connected to one of electrodes of the capacitor and an input of the inverter, and
wherein an output of the inverter is electrically connected to the first wiring.
3. The latch circuit according to claim 1 , wherein the transistor controls writing of data into a gate capacitor of the inverter.
4. The latch circuit according to claim 1 , wherein the transistor has a function of holding data in a gate capacitor of the inverter.
5. The latch circuit according to claim 1 , wherein the transistor controls writing of data into the capacitor.
6. The latch circuit according to claim 1 , wherein the transistor has a function of holding data in the capacitor.
7. The latch circuit according to claim 1 , wherein the first element is a NAND, and the second element is a clocked inverter.
8. A latch circuit comprising:
a latch portion; and
a data holding portion for holding data of the latch portion,
the latch portion comprising:
a first inverter; and
a second inverter,
wherein an output of the first inverter is electrically connected to an input of the second inverter, and an output of the second inverter is electrically connected to an input of the first inverter, and
wherein the input of the first inverter is electrically connected to a first wiring configured to be supplied with an input signal, and the output of the first inverter is electrically connected to a second wiring configured to be supplied with an output signal,
the data holding portion comprising:
a transistor;
a capacitor; and
a third inverter,
wherein a channel formation region of the transistor includes an oxide semiconductor layer,
wherein an input of the third inverter is electrically connected to the capacitor,
wherein the third inverter includes an n-channel transistor and a p-channel transistor, and
wherein one of a source and a drain of the transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the transistor is electrically connected to the input of the third inverter, and
wherein an output of the third inverter is electrically connected to the first wiring.
9. The latch circuit according to claim 8 , wherein the oxide semiconductor layer contains indium, gallium, and zinc.
10. The latch circuit according to claim 8 , wherein the transistor controls writing of data into a gate capacitor of the third inverter.
11. The latch circuit according to claim 8 , wherein the transistor has a function of holding data in a gate capacitor of the third inverter.
12. A circuit comprising:
a first element;
a second element;
a first transistor;
a second transistor; and
a capacitor,
wherein an output of the first element is electrically connected to an input of the second element, and an output of the second element is electrically connected to an input of the first element, and
wherein the input of the first element is electrically connected to a first wiring configured to be supplied with an input signal, and the output of the first element is electrically connected to a second wiring configured to be supplied with an output signal,
wherein a channel formation region of the first transistor includes an oxide semiconductor layer, and
wherein one of a source and a drain of the first transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to one of electrodes of the capacitor and a gate of the second transistor, and
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring.
13. The circuit according to claim 12 , wherein the oxide semiconductor layer contains indium, gallium, and zinc.
14. The circuit according to claim 12 , wherein the first transistor controls writing of data into the capacitor.
15. The circuit according to claim 12 , wherein the first transistor has a function of holding data in the capacitor.
16. The circuit according to claim 12 , wherein the first element is a NAND, and the second element is a clocked inverter.
17. The circuit according to claim 12 , further comprising a switch between the first element and the first wiring.
18. The circuit according to claim 12 , further comprising a switch between the second element and the first wiring.
19. The circuit according to claim 12 , further comprising a switch between the one of the source and the drain of the second transistor and the first wiring.