Metadata storage associated with wear-level operation requests
View Patent ↗A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.
1. A method comprising:
responding to a wear-level operation request by:
copying data from a first portion of a first memory array to a second portion of the first memory array, wherein the first memory array comprises a NAND or NAND-based memory array; and
copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array, wherein the second memory array comprises non-volatile memory comprising at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.
2. The method of claim 1 , wherein said copying data and copying metadata are performed in parallel with one another.
3. The method of claim 1 , wherein the wear-level operation request is received by a flash translation layer from a processor operationally connected to the flash translation layer.
4. The method of claim 1 , wherein the wear-level operation request is initiated by a flash translation layer.
5. The method of claim 1 , wherein said copying data comprises modifying an address from identifying the first portion of the first memory array to identifying the second portion of the first memory array.
6. The method of claim 1 , wherein said copying data comprises copying information from a first memory block of the first memory array to a second memory block of the first memory array.
7. The method of claim 6 , wherein the first memory block and the second memory block are both in a main area of the first memory array.
8. The method of claim 1 , wherein said copying metadata comprises copying the metadata from a third memory block of the second memory array to a fourth memory block of the second memory array.
9. The method of claim 1 , wherein the metadata comprises sector numbers, virtual block addresses, or both, of the NAND or NAND-based memory array.
10. The method of claim 1 , further comprising setting a flag to indicate that the first portion of the first memory array is invalid, to indicate that the first portion of the first memory array no longer stores valid data, or both.
11. The method of claim 10 , wherein the flag is stored in the second memory array.
12. A memory device comprising:
a NAND or NAND-based memory array;
a nonvolatile memory comprising at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory; and
a flash translation layer configured to respond to a wear-level operation request by:
copying data from a first portion of the NAND or NAND-based memory array to a second portion of the NAND or NAND-based memory array; and
copying metadata associated with the data from a third portion of the nonvolatile memory to a fourth portion of the nonvolatile memory.
13. The memory device of claim 12 , wherein said copying data and copying metadata are performed in parallel with one another.
14. The memory device of claim 12 , wherein the flash translation layer comprises a NAND driver and a PCM driver.
15. The memory device of claim 12 , wherein the metadata comprises sector numbers, virtual block addresses, or both, of the NAND or NAND-based memory array.
16. The memory device of claim 12 , wherein the flash translation layer comprises a wear-leveling module configured to monitor and evenly distribute a number of erase cycles per block of memory of the NAND or NAND-based memory array.
17. The memory device of claim 12 , wherein the first portion of the NAND or NAND-based memory array and the second portion of the NAND or NAND-based memory array are both in a main area of the NAND or NAND-based memory array.
18. The memory device of claim 12 , wherein the flash translation layer is further configured to set a flag to indicate that the first portion of the NAND or NAND-based memory array is invalid, to indicate that the first portion of the NAND or NAND-based memory array no longer stores valid data, or both.
19. The memory device of claim 18 , wherein the flag is stored in the nonvolatile memory.
20. A system comprising:
a computer processor; and
a memory device operationally coupled to the computer processor, the memory device comprising:
a NAND or NAND-based memory array;
a nonvolatile memory comprising at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory; and
a flash translation layer configured to respond to a wear-level operation request by;
moving data from a first portion of the NAND or NAND-based memory array to a second portion of the NAND or NAND-based memory array; and
moving metadata associated with the data from a third portion of the nonvolatile memory to a fourth portion of the nonvolatile memory.
21. The system of claim 20 , wherein said moving data and moving metadata are performed in parallel with one another.
22. The system of claim 20 , wherein the wear-level operation request is received by the flash translation layer from the computer processor.
23. The system of claim 20 , wherein the wear-level operation request is initiated by the flash translation layer.
24. The system of claim 20 , wherein said moving data comprises modifying an address from identifying the first portion of the NAND or NAND-based memory array to identifying the second portion of the NAND or NAND-based memory array.
25. The system of claim 20 , wherein said moving data comprises moving information from a first memory block of the NAND or NAND-based memory array to a second memory block of the NAND or NAND-based memory array.
26. The system of claim 25 , wherein the first memory block and the second memory block are both in a main area of the NAND or NAND-based memory array.
27. The system of claim 20 , wherein said moving metadata comprises moving the metadata from a third memory block of the nonvolatile memory to a fourth memory block of the nonvolatile memory.
28. The system of claim 20 , wherein the flash translation layer is further configured to set a flag to indicate that the first portion of the NAND or NAND-based memory array is invalid, to indicate that the first portion of the NAND or NAND-based memory array no longer stores valid data, or both.