IP Library Granted Patent US 9,081,710
Granted Patent B2
US 9,081,710 · App. 13/860,542 · Granted Jul 14, 2015

Restoring ECC syndrome in non-volatile memory devices

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Quick Facts
Patent No.
US 9,081,710
App. No.
13/860,542
Granted
Jul 14, 2015
Kind
B2
Abstract

A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method comprising identifying a first sector including at least one page having a disabled ECC (error correction code) flag; reading the value of all data bits in said at least one page; calculating values for ECC bits in said at least one page; and writing said data bit values and said calculated ECC bit values to a second sector in the memory cell array.

Claims (40)

1. A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method comprising:

identifying a first sector including at least one page having a disabled ECC (error correction code) flag;

reading the value of all data bits in said at least one page;

calculating values for ECC bits in said at least one page;

writing said data bit values and said calculated ECC bit values to a second sector in the memory cell array, and

erasing said second sector prior to writing said data bit values and said calculated ECC bit values from said first sector.

2. The method according to claim 1 further comprising:

reading all pages in said first sector;

identifying all pages having disabled ECC flags;

for all other pages in said first sector having disabled ECC flags:

reading the value of all data bits in each one of said all other pages;

calculating values for ECC bits in each one of said all other pages; and

writing said data bit values and said calculated ECC bit values to said second sector.

3. The method according to claim 1 further comprising:

identifying in said first sector all pages having an enabled ECC flag;

reading the values of all data bits and ECC bits in said pages having an enabled ECC flag;

correcting any incorrect data bit values in said data bits using said ECC bits; and

writing said data bit values including corrected data bit values and said ECC bit values in said pages having an enabled ECC flag to said second sector.

4. The method according to claim 1 further comprising erasing said first sector.

5. The method according to claim 1 further comprising swapping the physical addresses of said first and second sectors.

6. A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method comprising:

identifying a first sector including at least one page having a disabled ECC (error correction code) flag;

reading the value of all data bits in said at least one page;

calculating values for ECC bits in said at least one page;

writing said data bit values and said calculated ECC bit values to a second sector in the memory cell array; and

swapping the physical addresses of said first and second sectors.

7. The method according to claim 6 further comprising:

reading all pages in said first sector;

identifying all pages having disabled ECC flags;

for all other pages in said first sector having disabled ECC flags:

reading the value of all data bits in each one of said all other pages;

calculating values for ECC bits in each one of said all other pages; and

writing said data bit values and said calculated ECC bit values to said second sector.

8. The method according to claim 6 further comprising:

identifying in said first sector all pages having an enabled ECC flag;

reading the values of all data bits and ECC bits in said pages having an enabled ECC flag;

correcting any incorrect data bit values in said data bits using said ECC bits; and

writing said data bit values including corrected data bit values and said ECC bit values in said pages having an enabled ECC flag to said second sector.

9. The method according to claim 6 further comprising erasing said first sector.

10. The method according to claim 6 further comprising erasing said second sector prior to writing said data bit values and said calculated ECC bit values from said first sector.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2019
From: CYPRESS SEMICONDUCTOR CORPORATION
To: LONGITUDE FLASH MEMORY SOLUTIONS LIMITED
Reel/Frame 050799/0215 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Sep 26, 2019
From: MUFG UNION BANK, N.A., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 050500/0369 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 2, 2016
From: BLOOM, ILAN; GIVANT, AMICHAI; YOGEV, YOAV; SHEFI, AMIT
To: SPANSION LLC
Reel/Frame 039625/0279 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2015
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 035945/0766 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2013
From: BLOOM, ILAN; GIVANT, AMICHAI; YOGEV, YOAV; SHEFI, AMIT
To: SPANSION LLC
Reel/Frame 030639/0491 →